Dynamic Prescaling Counter for Overflow-Resistant Event Counting
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Solution Overview
Problem
Existing counters face issues with data loss due to overflow, which can be mitigated by using larger counters, but this increases power consumption and reduces operation speed, while prescalers reduce overflow but at the expense of precision, especially when event frequencies vary unpredictably.
Innovation Solution
A dynamic prescaling counter that adjusts its prescaling in response to the input count, using a programmable divider and registers to increment counters dynamically, allowing for a wide range of count results without processor logic, thus maintaining high clock speeds and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger counter is used to reduce overflow, then the counting range is increased, but the power consumption increases and the operation speed decreases
Solution Approach 1:
The counter is divided into two separate counters: a first counter that counts at full clock speed without prescaling, and a second counter that counts prescaled events. This segmentation allows the system to achieve extended counting range without requiring a single large counter, thereby maintaining lower power consumption and higher operation speed while preventing overflow.
Solution Approach 2:
The patent implements a nested counting structure where the second counter counts the overflow events of the first counter. The first counter operates within its native range, and when it overflows, the second counter increments to record the overflow occurrence. This nesting allows the system to effectively count beyond the first counter's range while keeping both counters small and efficient.
2Reliability
If a prescaler is used to reduce overflow, then the counting range is extended, but the measurement precision is reduced
Solution Approach 1:
The counting system is segmented into two independent counting paths: one that maintains full precision by counting every event directly, and another that uses prescaling to extend the range. The first counter preserves measurement precision for high-frequency events, while the second counter handles the extended range requirement, thus resolving the contradiction between precision and range.
Solution Approach 2:
The patent introduces an intermediary mechanism where the second counter acts as a mediator to record overflow events from the first counter. This intermediary approach allows the system to maintain high precision in the primary counting path while using the secondary path to extend the effective counting range, avoiding direct precision loss from prescaling.
3Reliability
If a fixed prescaler value is set to avoid overflow, then data loss is prevented, but precision is sacrificed when event frequency varies
Solution Approach 1:
The patent implements a dynamic dual-counter system where the first counter operates at full resolution for high-precision measurement, and the second counter dynamically tracks overflow events. This dynamic architecture adapts to varying event frequencies automatically, maintaining data integrity across different operating conditions without requiring manual prescaler adjustment.
Solution Approach 2:
The dual-counter architecture provides universal functionality that handles multiple event frequency scenarios. The first counter handles normal operating conditions with high precision, while the second counter activates during overflow conditions to extend the range. This multi-functional design adapts to both low and high event frequencies without sacrificing data integrity or precision.
Data Source
AI summary
A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.