Dynamic Priority Bus Arbiter for Image Processing Congestion
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Solution Overview
Problem
In imaging devices, the increased demand for high-definition image processing leads to congestion in the data bus, causing low-priority processing blocks to fail in completing their tasks within the specified time, which can result in system failures due to inadequate bus arbitration mechanisms that do not consider the timing of access requests effectively.
Innovation Solution
A memory access device that includes a data processor, a priority switching control part, and a bus arbiter, which calculates the remaining processing time and determines the urgency of data processing to dynamically adjust the priority of access requests, ensuring that even low-priority processing blocks can complete their tasks within the predetermined time by arbitrating access to the memory based on a priority switching signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration is performed based on priority in a state where the amount of access to the DRAM is large and the data bus is congested, then access requests from processing blocks with high priority can be reliably accepted, but access requests from processing blocks with lower priority will be less accepted
Solution Approach 1:
The patent implements dynamic priority adjustment by monitoring the remaining processing time of each processing block. When a low-priority processing block's remaining time approaches a predetermined threshold, its priority is automatically increased to ensure timely completion. This dynamic mechanism allows the arbitration circuit to adapt priority levels based on real-time processing status, resolving the contradiction between maintaining high-priority access reliability and ensuring low-priority blocks complete within specified time.
Solution Approach 2:
The patent employs a feedback mechanism where the arbitration circuit continuously monitors the remaining processing time of each processing block and adjusts arbitration decisions accordingly. The circuit receives feedback about processing progress and uses this information to dynamically modify priority assignments, ensuring that time-critical low-priority blocks receive adequate bus access while maintaining overall system reliability for high-priority operations.
2Productivity
If the number of processing blocks increases to support higher definition image processing, then the processing capability is improved, but the bus bandwidth required for each processing block increases rapidly causing data bus congestion
Solution Approach 1:
The patent applies dynamic priority adjustment to manage bus access among multiple processing blocks. By continuously monitoring remaining processing time and adjusting priorities in real-time, the system optimizes bus bandwidth allocation to support increased processing capability while minimizing access time delays caused by congestion.
Solution Approach 2:
The patent changes the arbitration parameter from static priority to dynamic priority based on remaining processing time. This parameter change allows the system to adapt to varying processing loads and bus congestion conditions, enabling efficient utilization of bus bandwidth across multiple processing blocks supporting high-definition image processing.
Data Source
AI summary
A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.