Dynamic Priority Bus Arbitration for Resource Conflict Resolution

Solution Overview

Problem

Existing system LSI technologies face challenges in optimizing resource conflict among circuit modules, particularly in real-time applications, due to variations in target resource usage timing, leading to inefficient resource utilization and performance issues.

Innovation Solution

An information processing device with a bus master circuit and arbiter system that dynamically adjusts access priorities and permissions based on storage units and control units, allowing flexible resource allocation and tolerance for timing variations without significantly affecting operating frequencies or circuit scale.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a round-robin method is used for bus arbitration, then the circuit scale is small and implementation is simple, but the target resource usage amount cannot be compensated for each master when request timing varies

Engineering Contradiction:

Improvecircuit scaleVSAvoidtarget resource usage amount compensation

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic priority adjustment in the bus arbitration system. The priority of each master is not fixed but changes based on its current resource usage amount and request timing. The arbitration circuit dynamically modifies priority levels to ensure that each master receives its allocated target resource usage amount even when request timing varies, resolving the contradiction between simple circuit implementation and effective resource compensation.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the priority parameter of masters dynamically based on their resource usage statistics. By monitoring and adjusting the priority parameter according to actual usage patterns and timing variations, the system ensures that each master achieves its target resource usage amount while maintaining a relatively simple arbitration circuit structure.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If fixed time-sharing priority allocation is used, then the target resource usage amount can be precisely compensated for each master, but the target resource is not effectively utilized when masters cannot output requests in their prioritized cycles

Engineering Contradiction:

Improvetarget resource usage amount compensationVSAvoidtarget resource utilization efficiency

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic priority adjustment in the bus arbitration system. The priority of each master is not fixed but changes based on its current resource usage amount and request timing. The arbitration circuit dynamically modifies priority levels to ensure that each master receives its allocated target resource usage amount even when request timing varies, resolving the contradiction between simple circuit implementation and effective resource compensation.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms that monitor the actual resource usage of each master and adjust priorities accordingly. This feedback loop allows the system to maintain precise resource compensation while adapting to varying request patterns, preventing resource waste when masters cannot output requests in their prioritized cycles.

Inventive Principle:

Principle #23Feedback

3Ease of operation

If priority is fixed for each master, then resource allocation is simple to control, but the system cannot tolerate variation in timing of target resource use requests

Engineering Contradiction:

Improveresource allocation controlVSAvoidtiming variation tolerance

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent implements dynamic priority adjustment in the bus arbitration system. The priority of each master is not fixed but changes based on its current resource usage amount and request timing. The arbitration circuit dynamically modifies priority levels to ensure that each master receives its allocated target resource usage amount even when request timing varies, resolving the contradiction between simple circuit implementation and effective resource compensation.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7337251B2Information processing device with priority-based bus arbitration

Publication Date: 2008.02.26 RENESAS ELECTRONICS CORP

AI summary

The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access rights, and an arbitration control logical unit for arbitrating the access rights of the master circuits based on the information. When the priority of the first master circuit is higher than the priority of the second master circuit and there is no access request from the first master circuit but there is an access request from the second master circuit, the arbitration control logical unit permits access of the second master circuit, and the storage units lower the priority of the second master circuit without changing the priority of the first master circuit.