Dynamic Processing Memory Core On-Chip Integration
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Solution Overview
Problem
The processor industry faces challenges due to the plateauing of transistor size reduction, leading to increased power consumption and cost as conventional processors rely on off-chip memory access, which slows performance and increases energy usage, especially with the incorporation of GPUs limited to rendering objects into triangles.
Innovation Solution
Incorporating a dynamic processing memory core onto a single memory chip, enabling both computational processing and memory storage, where a configurable processor controller transitions the core between processing and storage modes to optimize data access and reduce off-chip data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processors access conventional memory positioned off-chip, then memory capacity is sufficient, but processing performance slows and power consumption increases
Solution Approach 1:
The patent merges processing devices and memory storage devices onto a single chip to form an integrated processing memory system. This consolidation eliminates off-chip data transfers, thereby improving processing performance while reducing power consumption associated with external memory access.
Solution Approach 2:
The processing memory core is designed to dynamically function as both a memory storage device and a processing device based on operational mode. This multi-functionality allows the same hardware resources to serve dual purposes, improving overall system efficiency and reducing the need for separate dedicated components.
2Productivity
If the quantity of conventional processors positioned on a conventional chip is increased, then processing capabilities improve, but die space for memory access technologies increases
Solution Approach 1:
By integrating processing devices and memory storage devices on the same chip, the patent eliminates the need for separate memory access technologies and their associated die space. This consolidation maintains processing capabilities while reducing overall die space requirements.
Solution Approach 2:
The processing memory core can dynamically switch between operating as memory and operating as processing units. This multi-functionality allows the system to maintain high processing capabilities without requiring dedicated memory infrastructure, thereby reducing die space consumption.
3Adaptability or versatility
If conventional GPUs are incorporated into the conventional processor system, then graphical processing capabilities are enhanced, but power consumption and system cost increase
Solution Approach 1:
The processing memory core can be dynamically configured to perform both traditional memory functions and graphical processing functions. This eliminates the need for separate GPU hardware, reducing power consumption while maintaining graphical processing capabilities through software-defined functionality.
4Adaptability or versatility
If conventional GPUs are positioned off-chip, then graphical rendering capabilities are provided, but system cost and power consumption significantly increase
Solution Approach 1:
The patent integrates graphical processing capabilities directly into the processing memory core on the same chip, eliminating the need for separate off-chip GPU components. This consolidation reduces system complexity and cost while maintaining graphical rendering capabilities through the dynamic processing memory core.
Data Source
AI summary
Embodiments of the present invention provide a method for incorporating a dynamic processing memory core into a single memory chip to enable computational processing and memory storage from the single memory chip. The method includes storing data elements by memory storage devices positioned on the single memory chip. The method also includes executing, by a processing devices positioned on the single memory chip, memory instructions. The method also includes transitioning the dynamic memory processing core from a memory storage device to a processing device by instructing the processing device to execute the memory instructions. The method also includes transitioning the dynamic processing memory core from the processing device to the memory storage device by instructing the processing device to not execute the memory instructions thereby terminating the computational processing of the dynamic processing memory core and maintaining the memory storage provided by the memory storage device.


