Dynamic Processor Interface Connectivity via Software Schedules

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Solution Overview

Problem

In data processing devices with multiple processors, ensuring that ingress data is delivered to the appropriate processor and egress data is delivered to the correct interface for output is challenging due to the lack of fixed physical connectivity between processors and interfaces, requiring dynamic control through code-loaded schedules.

Innovation Solution

The implementation of a data processing device with multiple processors, each equipped with instruction memory and switching circuitry that connects to different buses based on schedules defined in local programs, allowing for dynamic association of processors with interfaces for data reception and transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple interfaces are provided to enable communication with different external devices, then the adaptability and connectivity of the system is improved, but the complexity of routing ingress data to appropriate processors and egress data to correct interfaces increases

Engineering Contradiction:
ImproveconnectivityVSAvoidrouting complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic connectivity by allowing processors to be associated with different interfaces through software schedules rather than fixed physical wiring. The schedule stored in each processor dynamically determines which interface the processor connects to during different execution phases, enabling flexible reconfiguration of data paths without hardware changes.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces a schedule as an intermediary mechanism between the physical hardware and the data routing logic. This schedule acts as a mediator that translates the physical interface connections into logical data paths, allowing the system to route data dynamically based on software control rather than fixed hardware topology.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If fixed physical connectivity is used between processors and interfaces, then the device complexity is reduced, but the adaptability to change data paths and routing configurations is limited

Engineering Contradiction:
Improveconnectivity structureVSAvoidrouting flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent replaces static physical connectivity with dynamic software-controlled connectivity. Each processor stores a schedule that dynamically assigns interface associations based on execution phase, allowing the same physical hardware to support multiple different data routing configurations without changing the physical structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of interface association from fixed hardware-level connections to variable software-level assignments. By modifying the schedule parameters in processor instructions, the system can reconfigure data paths and routing without physical hardware changes, achieving flexibility through parameter modification rather than structural change.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11940940B2External exchange connectivity
Publication Date: 2024.03.26 GRAPHCORE LTD
  • US11940940B2 patent drawing
  • US11940940B2 patent drawing
  • US11940940B2 patent drawing

AI summary

A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.