Dynamic Program-Erase Window for NAND Endurance
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Solution Overview
Problem
NAND flash memory faces limitations due to finite program-erase cycles, program or read disturb, and charge loss, which affect its endurance and reliability, especially as it undergoes cycling operations.
Innovation Solution
Implementing a dynamic program-erase window that varies with cycle count by adjusting the erase verify and program verify voltages, allowing for a smaller window initially to reduce charge fluence and trap-up, and using trim profiles to manage these changes based on cycle counts or failure triggers, thereby improving endurance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed program-erase window is used to meet end-of-life disturb and charge loss requirements, then reliability is improved, but cycling endurance deteriorates due to excessive charge fluence and trap-up during initial cycles
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed program-erase window to a dynamic window that shifts downward as a function of cycle count. The window position is adjusted based on accumulated cycling history, allowing the system to optimize between initial cycle protection and end-of-life reliability requirements. This dynamic adjustment reduces charge fluence and trap-up during early cycles while maintaining adequate margins at end of life.
Solution Approach 2:
The patent changes the parameter of window position (voltages defining the program and erase verify thresholds) as a function of cycle count. By modifying these voltage parameters dynamically based on cycling history, the system adapts the program-erase window to reduce harmful charge fluence and trap-up effects while maintaining reliability throughout the device lifecycle.
2Reliability
If a larger program-erase window is used to provide sufficient margin for disturb and charge loss, then reliability is improved, but power consumption increases due to higher charge fluence during cycling
Solution Approach 1:
The dynamic window adjustment allows the system to use a smaller program-erase window during initial cycling phases when less margin is needed, thereby reducing charge fluence and power consumption. As cycling progresses and reliability margins naturally degrade, the window is shifted to provide increased protection, optimizing the trade-off between power consumption and reliability throughout the device lifecycle.
Solution Approach 2:
By changing the voltage parameters that define the program-erase window based on cycle count, the system dynamically adjusts the charge fluence applied during cycling. This parameter change enables reduced power consumption during early cycles while maintaining adequate reliability margins, and increases protection during later cycles when margins have degraded.
3Manufacturing precision
If higher erase voltage is applied to ensure complete erasure, then manufacturing precision is improved, but trap-up increases reducing cycling endurance
Solution Approach 1:
The patent applies dynamics by adjusting the erase verify voltage threshold as a function of cycle count. During initial cycles, a higher erase verify threshold ensures complete erasure and manufacturing precision. As cycling progresses and trap-up accumulates, the dynamic window shift effectively reduces the applied erase stress, thereby reducing additional trap-up and preserving cycling endurance while maintaining adequate erasure completeness throughout the device lifecycle.
Data Source
AI summary
Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.