Dynamic Program Verify Pairing in Multi-Level Cell Memory

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Solution Overview

Problem

In multi-level cell memory devices, the increasing number of programming levels leads to a significant increase in programming time due to the need for separate program verify phases for each level, which negatively impacts performance and quality of service, especially when programming levels do not align with predefined static pairings or occur in odd numbers.

Innovation Solution

Implementing dynamic level pairing, where control logic pairs any two or more programming levels to be verified together, and an 'always paired' approach to ensure all levels are verified in pairs, reducing the need for individual verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If separate program verify phases are performed for each programming level, then verification accuracy is improved, but programming time increases significantly

Engineering Contradiction:

Improveverification accuracyVSAvoidprogramming time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent combines multiple programming levels into paired groups and performs verify operations on both levels simultaneously within a single program verify phase. This merging approach maintains verification accuracy for each level while reducing the total number of separate verify phases needed, thereby decreasing overall programming time.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic level pairing where the control logic adaptively pairs programming levels based on their thresholds and characteristics. This dynamic approach allows flexible grouping of levels that can be verified together, optimizing the verify process to maintain accuracy while minimizing time loss through intelligent level combination.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If static pairings are used for program verify operations, then device complexity is reduced, but adaptability to different programming level configurations is limited

Engineering Contradiction:

Improveverify operation structureVSAvoidprogramming level configuration flexibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent employs dynamic level pairing where the control logic determines optimal pairings based on the actual programming levels present and their threshold characteristics. This dynamic system adapts to different programming level configurations (such as odd numbers of levels or non-aligned levels) while maintaining a relatively simple verify operation structure through automated pairing logic.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the pairing parameters dynamically based on the programming level configuration. Instead of fixed static pairings, the system adjusts which levels are paired together based on their thresholds and the specific verify requirements, enabling adaptability to various configurations while keeping the underlying verify mechanism simple.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If individual programming level verifies are supported, then verification completeness is improved, but device complexity and operational overhead increase

Engineering Contradiction:

Improveverification completenessVSAvoidverify operation support structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges individual level verifies into paired verify operations, where each verify phase handles multiple programming levels simultaneously. This approach maintains verification completeness by ensuring each level is verified while reducing device complexity by eliminating the need for separate individual verify support structures for each level.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal paired verify mechanism that can handle verification for multiple programming levels through a single standardized process. This multi-functional approach replaces the need for level-specific verify operations, reducing operational overhead and device complexity while maintaining complete verification coverage.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230170033A1Program verify pairing in a multi-level cell memory device

Publication Date: 2023.06.01 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device initiates a first loop of a program operation, the first loop comprising (a) a program phase where a plurality of memory cells associated with a selected wordline in a block of the memory array are programmed to respective ones of a plurality of programming levels and (b) a corresponding program verify phase. The control logic further identifies memory cells of the plurality of memory cells associated with a first sub-set of the plurality of programming levels to be verified during the program verify phase, the first sub-set comprising two or more dynamically selected programming levels comprising at least a lowest programming level and a second lowest programing level of the respective ones of the plurality of programming levels. The control logic further causes a first program verify voltage to be applied to the selected wordline during the program verify phase, and performs concurrent sensing operations on the identified memory cells of the plurality of memory cells associated with the first sub-set of the plurality programming levels to determine whether the identified memory cells were programmed to respective program verify threshold voltages corresponding to the first sub-set of the plurality of programming levels during the program phase of the first loop of the program operation.