Dynamic Programming Pulse Duration Adjustment in Memory Devices
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Solution Overview
Problem
Existing semiconductor memory programming techniques face inefficiencies due to variations in word line ramping times, leading to suboptimal programming performance and reliability.
Innovation Solution
A method and apparatus for dynamically adjusting the programming pulse duration in semiconductor memory devices by checking the selected word line voltage at multiple checkpoints and comparing it to the programming voltage, allowing for optimized pulse durations based on ramping speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed programming pulse duration is used for all word lines, then programming reliability is maintained for slow word lines, but programming performance deteriorates for fast and average word lines
Solution Approach 1:
The patent implements dynamic adjustment of programming pulse duration based on the actual ramping speed of each word line. The system transitions from a static, fixed pulse duration approach to a dynamic one where the pulse duration is adapted in real-time according to measured word line characteristics, thereby resolving the contradiction between maintaining reliability for slow word lines and improving performance for fast word lines
Solution Approach 2:
The patent changes the programming parameter (pulse duration) based on the observed ramping behavior of word lines. By measuring the time required for word line voltage to reach the programming voltage and adjusting the pulse duration accordingly, the system optimizes programming performance while ensuring adequate programming for all word line types
2Productivity
If the programming pulse duration is shortened to improve performance, then programming speed increases for fast word lines, but programming reliability deteriorates for slow word lines
Solution Approach 1:
The patent dynamically changes the programming pulse duration parameter based on measured word line ramping characteristics. Fast word lines receive shorter pulse durations to improve speed, while slow word lines receive adequate pulse durations to maintain reliability, thus resolving the contradiction between programming speed and reliability
3Measurement precision
If multiple checkpoints are used to monitor word line voltage, then programming precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the programming process into multiple checkpoints where word line voltage is monitored at specific intervals. This segmentation allows precise measurement of ramping speed without requiring continuous monitoring, thereby achieving high measurement precision while limiting the increase in device complexity to discrete monitoring points rather than continuous complex control circuitry
Data Source
AI summary
The memory device includes a memory block with an array of memory cells that are arranged in word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line in a plurality of program loops. In at least one of the program loops, the circuitry is configured to, for a programming pulse duration, ramp a selected word line voltage V_WLn to a programming voltage VPGM and then hold the selected word line voltage V_WLn at the programming voltage VPGM. In at least one checkpoint during the ramping of the selected word line voltage V_WLn to the programming voltage VPGM, the circuitry checks the selected word line voltage V_WLn and dynamically adjusts the programming pulse duration based on the check of the selected word line voltage V_WLn.