Dynamic Programming Verify Start for NAND Memory
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Solution Overview
Problem
The increasing number of bits stored in NAND memory cells leads to longer programming times, with programming verification operations being a significant contributor to this delay, particularly in Quad Level Cell (QLC) memory, where verification times account for more than half of the total programming time.
Innovation Solution
A dynamic programming verify start (DPVS) algorithm is introduced, which adapts the timing of programming verification based on the number of pass cells in the current state, and a two-step programming approach is implemented, using different preset values for coarse and fine programming to reduce the number of verification operations and optimize programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in NAND memory cells is increased, then the storage capacity is improved, but the programming time is extended
Solution Approach 1:
The patent segments the programming verification process into multiple phases (e.g., coarse programming verification and fine programming verification). Different verification strategies are applied to different phases, allowing the system to handle higher-density memory cells more efficiently by performing fewer verifications in early phases and more verifications in later phases when needed.
Solution Approach 2:
The patent dynamically changes verification parameters such as verification voltage levels, verification timing, and verification thresholds based on the programming state and memory cell characteristics. This adaptive parameter adjustment optimizes the balance between verification accuracy and programming speed for high-density memory cells.
2Reliability
If verification operations are performed frequently to ensure programming quality, then the reliability is improved, but the programming time is extended
Solution Approach 1:
The patent implements dynamic verification strategies where the verification frequency, timing, and criteria are adjusted based on real-time programming progress and memory cell state. The system transitions from less frequent verification in early programming stages to more frequent verification as programming approaches completion, optimizing both speed and quality.
Solution Approach 2:
The patent incorporates feedback mechanisms where verification results from earlier programming pulses inform subsequent verification decisions. The system uses verification outcomes to dynamically adjust future verification parameters, performing verifications only when necessary to ensure quality while minimizing overall programming time.
Data Source
AI summary
The present disclosure provides a method of operating a memory, a memory and a memory system. The method comprises: performing a plurality of first programming verification operations on a plurality of memory cells of the memory, to acquire a plurality of memory cells with a first programming state to an i-th programming state, wherein i is a positive integer; performing a second programming verification operation on the memory cells with a an n-th programming state, to acquire a second verification result for the memory cells with the n-th programming state, wherein n is a positive integer; if the second verification result for the memory cells with the n-th programming state is greater than or equal to a second preset value, performing the second programming verification operation on the memory cells with n+1 programming state, wherein the second preset value is different from the first preset value.