Dynamic Pulse Generator With Integrated Logic for Low Propagation Delay
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Solution Overview
Problem
Existing pulse generator designs result in significant time wastage due to propagation delays, primarily caused by the separation of static D flip-flops, AND gates, and buffers, which hinder immediate succession of clock pulses.
Innovation Solution
A dynamic pulse generator is proposed, integrating both sequential elements and pulse logic into a single stage using P-MOS and N-MOS transistors, along with digital CMOS and tri-state inverters, to minimize propagation delays by enabling programmable delay settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate static D flip-flop, AND gate, and buffer cells are used in pulse generator, then circuit design is simplified and modular, but propagation delay increases and pulse generation efficiency decreases
Solution Approach 1:
The patent combines the sequential element (D flip-flop) and pulse logic (AND gate and buffer) into a single integrated stage. The D flip-flop output directly drives the pulse generation logic without requiring separate buffer stages, eliminating the propagation delays that occur when signals pass through multiple discrete cell boundaries. This integration maintains design simplicity while significantly reducing the time lost to inter-cell signal transmission.
2Reliability
If static D flip-flop is used with inverter at clock input, then hold violations are avoided, but pulse generation speed decreases
Solution Approach 1:
The patent transitions from a static D flip-flop design to a dynamic pulse generation stage. The dynamic design allows the circuit to adapt its operation mode, using the D flip-flop for reliable hold violation prevention while incorporating direct pulse logic that can operate faster than traditional static approaches. The dynamic stage optimizes the balance between reliability and speed by selectively engaging different operational paths.
3Power
If large buffer is used to drive next stage, then signal driving capability is improved, but time wasted in buffer propagation increases
Solution Approach 1:
The patent eliminates the separate large buffer cell by integrating the buffering function directly into the pulse generation stage. The pulse logic is designed to directly drive the next stage without requiring an intermediate buffer, thereby maintaining sufficient signal driving capability while eliminating the propagation delay that would occur in a separate buffer cell. This integration removes the wasted time associated with buffer propagation.
4Device complexity
If AND gate and buffer are separate cells, then circuit modularity is maintained, but immediate pulse succession is hindered
Solution Approach 1:
The patent merges the AND gate and buffer into a single integrated pulse generation unit that operates in conjunction with the D flip-flop. This integration allows the circuit to maintain modularity at the stage level while eliminating the inter-cell delays that would prevent immediate pulse succession. The combined design enables pulses to be generated back-to-back without the time penalties associated with separate cell operations.
Data Source
AI summary
Embodiments of the invention provide for a dynamic pulse generator which can combine both the sequential element and the pulse logic into one stage, thereby eliminating the wasted time resulting from a pulse generator' input-to-output propagation delay. The dynamic pulse generator can include a plurality of P-MOS an N-MOS transistors, a first delay element, and a second delay element.