Dynamic RAID Memory Controller for Flexible Module Expansion
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Solution Overview
Problem
Conventional RAID systems face challenges with algorithmic layout approaches and flat virtual address spaces, making it difficult to dynamically expand or shrink memory modules, support modules of differing capacities, and efficiently manage data access latency.
Innovation Solution
The dynamic RAID scheme dynamically encodes RAID address space geometries, allowing for flexible mapping without static requirements, enabling dynamic expansion and contraction of memory systems, and supporting varied memory module capacities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a traditional algorithmic RAID mapping is used, then data stripes are systematically organized across memory modules, but the system becomes difficult to change and cannot dynamically expand or shrink memory modules
Solution Approach 1:
The patent applies dynamics by transitioning from a static algorithmic mapping to a dynamic mapping system. The memory controller now uses a data structure that can be modified at runtime, allowing memory modules to be added or removed without requiring complete system reconfiguration. The mapping evolves from fixed predetermined patterns to flexible dynamic assignments that adapt to changing system conditions.
Solution Approach 2:
The patent changes the parameter of memory mapping from fixed algorithmic rules to dynamic configurable parameters. The system now maintains a data structure containing mapping information that can be updated to reflect changes in memory module capacity, quantity, or configuration. This allows the same system to support different memory arrangements without hardware changes.
2Device complexity
If a flat virtual address space with fixed granularity is used, then addressing is simplified, but the system cannot support memory modules of differing capacities
Solution Approach 1:
The patent segments the flat virtual address space into multiple regions or zones, each capable of mapping to different memory modules with different capacities. Instead of treating all address space uniformly, the system divides it into manageable segments that can be independently configured to match the actual physical memory layout, supporting modules of varying sizes while maintaining manageable complexity.
Solution Approach 2:
The patent introduces an additional dimension to the addressing scheme by adding a layer of indirection through a data structure that maps virtual addresses to physical memory locations. This extra mapping layer allows the system to support heterogeneous memory capacities without increasing the fundamental addressing complexity, as the data structure handles the variation in module sizes.
3Ease of manufacture
If algorithmic mapping is used, then initial setup is straightforward, but runtime modifications such as expanding or shrinking memory modules become prohibitively difficult or expensive
Solution Approach 1:
The patent applies preliminary action by pre-allocating and pre-configuring memory regions and their mapping relationships before runtime. The system establishes a data structure that anticipates future memory configurations, allowing for smoother transitions when memory modules need to be added or removed. This preliminary setup reduces the complexity of runtime modifications compared to pure algorithmic mapping.
Data Source
AI summary
A memory controller is configured to receive segment pointers that identify physical memory devices and slices for associated segments. The memory controller is configured to identify a most-full first one of the physical memory devices, to identify a most-empty second one of the physical memory devices, and to identify one of the segments in the most-full first one of the physical memory devices. The memory controller is configured to move a slice from the identified one of the segments in the most-full first one of the physical memory devices to the most-empty second one of the physical memory devices. The memory controller is configured to update one of the segment pointers for the identified segment. The memory controller is configured to update one of the segment pointers for the identified segment by removing a previous segment pointer to the most-full first one of the physical memory devices.