Dynamic Read Data Return Size Adjustment for Interconnect Bus Utilization

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Solution Overview

Problem

The existing memory management systems face inefficiencies in optimizing read data return sizes on interconnect buses, leading to suboptimal utilization and increased bandwidth requirements, particularly when interconnect bus utilization exceeds certain thresholds.

Innovation Solution

A memory system and method that dynamically adjust read data return sizes based on interconnect bus utilization by tracking memory requests and detecting utilization thresholds, allowing for the selection of reduced read data sizes from predefined options to optimize traffic and reduce bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read data return sizes are increased to improve data transfer efficiency, then bandwidth utilization improves, but interconnect bus utilization exceeds thresholds causing system performance degradation

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidinterconnect bus utilization threshold
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic adjustment of read data return sizes based on real-time interconnect bus utilization monitoring. The memory controller continuously tracks bus utilization metrics and adapts the read data return size parameter accordingly, switching between different size configurations to maintain optimal performance while preventing threshold violations that would degrade system performance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of read data return size dynamically based on monitored bus utilization conditions. By adjusting this parameter in response to utilization thresholds, the system optimizes data transfer efficiency while preventing harmful overload conditions on the interconnect bus.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If read data return sizes are decreased to reduce interconnect bus utilization, then bandwidth requirements are reduced, but data transfer efficiency decreases

Engineering Contradiction:
Improveinterconnect bus utilizationVSAvoiddata transfer efficiency
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The system dynamically adjusts read data return sizes based on real-time monitoring of interconnect bus utilization. When utilization exceeds predefined thresholds, the system reduces read data return sizes to lower bandwidth requirements and prevent harmful overload conditions. When utilization is within acceptable ranges, the system increases read data return sizes to maximize data transfer efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by dynamically modifying the read data return size based on bus utilization metrics. This allows the system to optimize the balance between bandwidth consumption and transfer efficiency by adjusting the parameter in response to actual system conditions rather than using a fixed size.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If fixed read data return sizes are used to simplify memory controller logic, then device complexity is reduced, but system performance cannot be optimized under varying bus utilization conditions

Engineering Contradiction:
Improvememory controller logicVSAvoidsystem performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces dynamic adjustment capabilities to the memory controller, allowing it to adapt read data return sizes based on monitored bus utilization conditions. This dynamic approach enables the system to optimize performance under varying load conditions while maintaining manageable controller logic through structured monitoring and adjustment mechanisms.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9892066B1Dynamically adjusting read data return sizes based on interconnect bus utilization
Publication Date: 2018.02.13 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9892066B1 patent drawing
  • US9892066B1 patent drawing
  • US9892066B1 patent drawing

AI summary

A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.