Dynamic Read Retry Voltage Sequences for Memory Timeout Control
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Solution Overview
Problem
Memory subsystems suffer from reduced system performance due to inefficient read retry operations, which cannot send data to a host device while conducting read retries, leading to imbalanced performance and power consumption.
Innovation Solution
Dynamically selecting a read retry voltage sequence based on the likelihood of a read retry timeout, prioritizing speed when a timeout is likely and power efficiency when speed is a lower priority, using a voltage sequence selection manager to balance read retry latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read retry operations are used, then data reading can be attempted again after failure, but system performance deteriorates because the memory subsystem cannot send data to the host device during read retries
Solution Approach 1:
The patent applies dynamics by making the read retry voltage sequence configurable and adaptable based on system conditions. The memory subsystem controller can dynamically select between different voltage sequences (first sequence for speed, second sequence for power efficiency) depending on whether timeout is likely, transforming a static read retry process into a dynamic one that responds to real-time operational context.
Solution Approach 2:
The patent changes the voltage sequence parameter used during read retry operations. By switching between a first voltage sequence optimized for speed and a second voltage sequence optimized for power efficiency based on timeout likelihood, the system adjusts critical electrical parameters to resolve the contradiction between reliability and productivity.
2Reliability
If read retry operations are performed, then data retrieval reliability improves, but power consumption increases due to extended operation time
Solution Approach 1:
The patent directly addresses this contradiction by changing the voltage sequence parameter. When timeout is unlikely, the system uses a second voltage sequence that prioritizes power efficiency over speed, thereby reducing power consumption during read retry operations while still achieving successful data retrieval.
Solution Approach 2:
The system dynamically adapts its power consumption characteristics by selecting different voltage sequences based on timeout probability. This dynamic adjustment allows the memory subsystem to optimize power usage during read retries without sacrificing reliability, as the voltage sequence is selected based on real-time assessment of timeout likelihood.
3Device complexity
If a single fixed voltage sequence is used for read retries, then device complexity is reduced, but adaptability to different performance requirements deteriorates
Solution Approach 1:
The patent implements dynamics by introducing multiple voltage sequences that can be dynamically selected based on operational context. The memory subsystem controller assesses timeout likelihood and selects between a first voltage sequence (speed-optimized) and a second voltage sequence (power-optimized), enabling the system to adapt to different performance requirements without significantly increasing device complexity.
Solution Approach 2:
The patent applies universality by designing a read retry mechanism that can serve multiple performance objectives. The same read retry functionality can operate in speed-optimized mode or power-optimized mode depending on the selected voltage sequence, making the system versatile enough to handle different performance requirements while maintaining a unified control architecture.
Data Source
AI summary
Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.