Dynamic Read Threshold Adjustment for Memory Map Caching

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Solution Overview

Problem

Current memory systems face inefficiencies in caching map data, leading to reduced cache hit probabilities and increased operational burdens due to fixed read count thresholds, which result in degraded performance and increased cache misses.

Innovation Solution

A memory system that dynamically adjusts the read count threshold based on miss and provision counts, selectively caching memory map segments with high read frequencies and updating cache data to improve cache hit probabilities and reduce operational burdens.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a fixed read count threshold is used for caching map data, then the caching operation is simple, but the cache hit probability decreases and cache misses increase

Engineering Contradiction:
Improvecaching operation simplicityVSAvoidcache hit probability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies dynamics by transitioning from a fixed read count threshold to a dynamic threshold adjustment mechanism. The memory controller continuously monitors read counts of map segments and adjusts the threshold based on current system conditions and access patterns, allowing the caching strategy to adapt to changing workloads and improve cache hit probability while maintaining operational simplicity through automated control.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by having the memory controller monitor cache miss rates and read access patterns, then use this information to adjust the read count threshold. The system feeds back performance metrics (cache hit/miss counts) to the threshold adjustment mechanism, creating a closed-loop control system that optimizes caching performance based on actual system behavior.

Inventive Principle:
Principle #23Feedback

2Device complexity

If a fixed read count threshold is used, then the system complexity is low, but performance is degraded due to increased cache misses

Engineering Contradiction:
Improvesystem complexityVSAvoiddata access efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system transitions from a static threshold to a dynamic adjustment mechanism that adapts to changing access patterns. The memory controller automatically adjusts the read count threshold based on monitored performance metrics, enabling the system to optimize data access efficiency without requiring complex manual configuration or intervention.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The caching system performs self-optimization through automated threshold adjustment. The memory controller monitors its own performance metrics (cache misses, read counts) and autonomously adjusts the threshold parameter to improve performance, eliminating the need for external intervention or complex user configuration while maintaining low system complexity.

Inventive Principle:
Principle #25Self-service

3Productivity

If map data is not cached in the host, then the memory system must handle all address translation requests, but the host cannot achieve faster data access

Engineering Contradiction:
Improvedata access speedVSAvoidmemory system operational burden
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing map segments into two categories: frequently accessed segments that are cached in the host, and less frequently accessed segments that remain in the memory system. This segmentation allows the host to achieve faster access for hot data while the memory system retains responsibility for cold data, balancing performance improvement with operational burden reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The host cache acts as an intermediary between the host and the memory system for address translation. By caching frequently accessed map segments in the host, the system creates an intermediate layer that handles common translation requests locally, reducing the operational burden on the memory system while enabling faster data access for the host.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11200178B2Apparatus and method for transmitting map data in memory system
Publication Date: 2021.12.14 SK HYNIX INC
  • US11200178B2 patent drawing
  • US11200178B2 patent drawing
  • US11200178B2 patent drawing

AI summary

An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.