Dynamic Read Voltage Management for SSD Latency Reduction

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Solution Overview

Problem

The existing read latency in solid state drives (SSDs) is prolonged due to varying read voltages affected by program/erase cycles, data retention time, and physical inconsistencies in 3D Triple-Level Cell flash media, making it challenging to maintain a unified valid read voltage across layers.

Innovation Solution

A read latency reduction method that dynamically updates read voltage management information based on physical characteristics of storage areas, ensuring accurate read voltages for improved read success rates and reduced latency by allocating similar physical locations to the same storage area with corresponding read voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read voltage prefabrication table technology is used, then read success rate is improved, but read latency is reduced only slightly and workload becomes heavy

Engineering Contradiction:
Improveread success rateVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by transitioning from a static read voltage table to a dynamic read voltage adjustment mechanism. The system continuously monitors read success rates and automatically adjusts read voltages in real-time, allowing the storage device to adapt to changing conditions without requiring heavy pre-computed tables, thus reducing latency while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by establishing a closed-loop system where read operations are monitored and the results feed back into voltage adjustment decisions. The controller uses feedback from read success/failure rates to dynamically optimize read voltages, eliminating the need for heavy prefabrication tables while achieving both high reliability and low latency.

Inventive Principle:
Principle #23Feedback

2Reliability

If read voltage prefabrication table is formulated for different storage media, then read success rate improves, but device complexity and workload increase

Engineering Contradiction:
Improveread success rateVSAvoidworkload
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the storage device to automatically optimize its own read voltages without external intervention. The system self-adjusts voltages based on monitored read performance, eliminating the need for complex external table formulation and reducing overall device complexity while maintaining high read success rates.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses parameter changes by dynamically modifying read voltage parameters based on real-time performance monitoring. Instead of using fixed prefabrication tables, the system adapts voltage parameters on-the-fly, reducing computational workload and device complexity while achieving optimal read success rates for different storage media conditions.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If multiple read operations are performed to handle voltage drift, then read accuracy is maintained, but read latency increases

Engineering Contradiction:
Improveread accuracyVSAvoidread latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by proactively adjusting read voltages before actual read operations based on predicted drift patterns. The system pre-compensates for voltage changes by anticipating drift conditions and preparing optimal voltages in advance, allowing single-read operations to succeed without requiring multiple retry reads, thus maintaining accuracy while reducing latency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3702897B1Method and device for reducing reading latency
Publication Date: 2024.10.02 HUAWEI TECH CO LTD
  • EP3702897B1 patent drawingFigure 1A
  • EP3702897B1 patent drawingFigure 1B
  • EP3702897B1 patent drawingFigure 2~3

AI summary

Embodiments of this application provide a read latency reduction method and an apparatus, and relate to the field of data storage technologies, so as to reduce a read latency. The method is applied to a controller. A front end of the controller is connected to a host, and a back end of the controller is connected to a flash array. The method includes: receiving a read request sent by the host, where the read request includes location indication information of requested data; obtaining, from read voltage management information based on a first physical location indicated by the location indication information, a read voltage corresponding to a first storage area in which the first physical location is located, where the first physical location is a physical location of the requested data in the flash array, the flash array includes a plurality of storage areas, physical characteristics of a plurality of physical locations included in a same storage area are identical or similar, the read voltage management information includes a correspondence between a storage area and a read voltage, and the read voltage in the read voltage management information is dynamically updated; and obtaining the requested data based on the read voltage corresponding to the first storage area, and sending the requested data to the host.