Dynamic Redundancy Cell Block for Memory Error Correction
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, necessitating the use of repair methods or error correction techniques, but existing solutions do not efficiently utilize redundancy resources for error correction.
Innovation Solution
A memory device design that includes a memory cell array with normal cell blocks, an error correction code (ECC) cell block, and a redundancy cell block, where an error correction circuit selectively uses ECC codes from both blocks to correct errors, maximizing error correction capability without increasing the device area by utilizing unused redundancy resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy cell blocks are allocated for error correction, then error correction capability is improved, but device area increases
Solution Approach 1:
The redundancy cell block is designed to serve dual purposes: it can function as a repair resource for defective cells or as an additional ECC storage resource. The control circuit dynamically configures the redundancy cell block to store either repair information or second ECC data based on system needs, allowing one resource to fulfill multiple functions without increasing device area
Solution Approach 2:
The system changes the functional parameter of the redundancy cell block from a fixed repair-only role to a dynamic role that can store either repair information or second ECC data. This parameter change allows the same physical resources to provide enhanced error correction capability without requiring additional area
2Reliability
If more ECC codes are used to improve error correction capability, then reliability is improved, but device complexity increases
Solution Approach 1:
The error correction system implements dynamic configuration where the control circuit adjusts the operational mode based on the state of redundancy cell blocks. When redundancy blocks are available and not needed for repair, they are dynamically configured to store second ECC data, enabling the system to adaptively enhance error correction capability without permanent structural complexity
Solution Approach 2:
The system automatically determines whether redundancy cell blocks should store repair information or second ECC data based on their operational status. The control circuit autonomously configures the redundancy resources without external intervention, allowing the system to self-optimize its error correction capability while managing complexity internally
Data Source
AI summary
A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.