Dynamic Redundancy Registers for STT-MRAM Write Error Tolerance
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Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, leading to unreliable memory operations.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for data verification, re-write attempts, and data relocation within the memory bank, ensuring high write error rate tolerance without impacting throughput or random access addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic redundancy registers are implemented to verify and re-write data, then memory reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements nested redundancy registers (e1 register containing data words, e2 register containing backup data) within the memory device structure. The e1 register holds data words awaiting verification or re-write operations, while the e2 register provides backup storage. This nesting approach allows multiple levels of redundancy without requiring completely separate systems, thereby improving reliability while controlling complexity growth.
Solution Approach 2:
The redundancy functionality is segmented into distinct registers (e1 and e2) with specific roles. The e1 register handles active data words requiring verification or re-write, while the e2 register provides backup storage. This segmentation allows the system to manage complexity by dividing the redundancy function into manageable, specialized components rather than using a monolithic approach.
2Reliability
If data verification and re-write operations are performed, then data integrity is improved, but write speed decreases
Solution Approach 1:
The patent performs preliminary verification actions by storing data words in the e1 register before final write completion. This allows the system to prepare verification and re-write operations in advance, so that if verification fails, re-write operations can immediately proceed without delaying the overall write throughput. The preliminary staging of data in the e1 register enables fast retrieval for re-write attempts.
Solution Approach 2:
The patent creates copies of data words in the e1 and e2 registers to enable verification and re-write operations. By maintaining duplicate copies of data words in these redundancy registers, the system can perform verification without affecting the original write operation to the memory bank. If verification fails, the copied data can be re-written immediately, maintaining write speed while ensuring data integrity.
3Reliability
If multiple re-write attempts are allowed, then write error rate is reduced, but time consumption increases
Solution Approach 1:
The patent implements a configurable number of re-write attempts (e.g., up to 3 attempts) rather than allowing unlimited re-write operations. This partial action approach provides sufficient redundancy to handle typical write errors in STT-MRAM devices while limiting the time consumption associated with excessive re-write attempts. The configurable nature allows optimization between reliability and time consumption based on specific application requirements.
4Reliability
If power down flushing is implemented to secure data, then data security is improved, but power down time increases
Solution Approach 1:
The patent performs preliminary flushing of data from the e1 and e2 registers to the memory bank before the power down sequence completes. By initiating this flush operation early in the power down process, the system ensures that critical data is secured in non-volatile storage before power is completely removed. This preliminary action allows the majority of the flush to occur while power is still available, minimizing the extension of power down time.
Solution Approach 2:
The patent implements a prioritized flushing mechanism that rushes to secure the most critical data words first during the power down sequence. Rather than flushing all data uniformly, the system identifies and flushes high-priority data from the redundancy registers immediately, skipping less critical operations that can be deferred. This approach secures essential data quickly while minimizing overall power down time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables STT-MRAM devices to operate reliably with high write error rates by verifying and re-writing data words, maintaining data integrity and system performance even under conditions of write failures, thus enhancing memory reliability and stability.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
Data Source
AI summary
A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, and before the memory device is powered down, processing data words of the second plurality of data words and associated memory addresses through the pipeline to write data into the memory bank. Finally, the method comprises powering down the memory device.