Dynamic Redundancy Registers for STT-MRAM Write Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, leading to unreliable memory operations.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for data verification, re-write attempts, and data relocation within the memory bank, ensuring high write error rate tolerance without impacting throughput or random access addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If STT-MRAM devices use their inherently stochastic write mechanism, then write speed is maintained, but write error rate increases leading to unreliable memory operations
Solution Approach 1:
The patent implements preliminary verification actions by introducing verify registers that store expected data values before write operations. After writing data to STT-MRAM cells, the system retrieves stored values from verify registers and compares them with actual written data to detect write errors before they propagate, thus maintaining fast stochastic writes while ensuring reliability through pre-prepared verification data
Solution Approach 2:
The patent establishes a feedback mechanism where write operations are followed by verify operations that compare expected values (from verify registers) with actual written values. When write errors are detected, the system generates feedback signals to trigger re-write operations, creating a closed-loop control system that continuously monitors and corrects write errors while maintaining overall system speed
2Reliability
If verification and re-write operations are implemented to handle write errors, then reliability improves, but processing time and throughput may be impacted
Solution Approach 1:
The patent segments the memory system into multiple independent components including memory banks, verify registers, pipelines for write operations, and pipelines for verify operations. This segmentation allows write and verify operations to proceed in parallel through different pipeline stages, so that verification processes do not block subsequent write operations and overall throughput is maintained despite added reliability checks
Solution Approach 2:
The patent implements continuous operation by using pipelined architectures where write operations, verify operations, and re-write operations can overlap in time. While one operation is being verified, other write operations continue through the pipeline, ensuring that the system maintains continuous productive action rather than stalling to perform verification, thus preserving throughput while improving reliability
3Reliability
If dynamic redundancy registers are added for data verification and re-write operations, then write error rate tolerance improves, but device complexity increases
Solution Approach 1:
The patent designs verify registers to serve multiple functions: they store expected data values for verification, act as temporary storage during re-write operations, and provide data for error detection and correction. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while achieving improved write error rate tolerance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables STT-MRAM devices to operate reliably with high write error rates by verifying and re-writing data words, maintaining data integrity and system performance even with high write error rates.
Implementation Method 1
Magnetoresistive random-access memory ('MRAM') is a non-volatile memory technology that stores data through magnetic storage elements. These magnetic storage elements are two ferromagnetic plates or electrodes that can hold a magnetic field
Implementation Method 2
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers
Implementation Method 3
The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a '1' and a '0'
Data Source
AI summary
A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.