Dynamic Redundancy Registers for STT-MRAM Write Error Tolerance
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Solution Overview
Problem
Spin-transfer torque magnetic random access memory (STT-MRAM) devices suffer from high write error rates due to their inherently stochastic write mechanism, leading to unreliable memory operations.
Innovation Solution
The implementation of dynamic redundancy registers, specifically an e1 register and an optional e2 register, which allow for data verification, re-write attempts, and data relocation within the memory bank, ensuring high write error rate tolerance without compromising throughput or random access addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic redundancy registers are added to verify and re-write data, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a hierarchical register structure where e1 registers are nested within memory banks and e2 registers provide an additional layer of redundancy. Data flows through nested verification stages: first e1 register verification, then e2 register verification, creating a nested doll-like structure where each register type contains and protects the previous level's data.
Solution Approach 2:
The redundancy register system is segmented into multiple independent components: e1 registers for first-level verification, e2 registers for second-level verification, and associated control logic. This segmentation allows each component to be independently managed, verified, and replaced without affecting the entire memory system.
2Reliability
If multiple re-write attempts are performed, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary verification actions by storing data in e1 registers before committing to the memory bank. This preliminary action allows the system to detect write failures early and initiate re-write operations without completing full write cycles, saving time by avoiding unnecessary operations on doomed writes.
Solution Approach 2:
The verification mechanism provides immediate feedback on write success or failure. When a write fails verification in the e1 register, the system receives feedback and automatically triggers re-write attempts. This closed-loop feedback system optimizes time by only performing re-writes when actually needed, rather than using fixed retry sequences.
3Reliability
If data verification and re-write operations are implemented, then reliability is improved, but productivity decreases
Solution Approach 1:
The e1 and e2 registers serve as intermediary buffers between the memory bank and the external interface. These intermediaries absorb the overhead of verification and re-write operations, allowing them to occur without blocking the main memory throughput path. The intermediaries isolate the productivity-critical path from the reliability-enhancing but time-consuming verification processes.
Solution Approach 2:
The patent implements a mechanism where failed data words are discarded from the main throughput stream and recovered through separate re-write operations. When verification fails, the problematic data is discarded from the critical path and recovered through background re-write attempts using the redundancy registers, preventing failed operations from bottlenecking overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic redundancy registers enable reliable data storage and retrieval in STT-MRAM devices by verifying and re-writing data words that fail to write correctly, maintaining data integrity and system performance even with high write error rates.
Implementation Method 1
Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell changes due to the orientation of the magnetization of the two layers.
Implementation Method 2
The second plate is typically referred to as the free layer and its magnetization direction can be changed by a smaller magnetic field or spin-polarized current relative to the reference layer.
Data Source
AI summary
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein the memory bank comprises a total of B entries, and wherein the memory cells are characterized by having a prescribed word error rate, E. Further, the device comprises a pipeline comprising M pipestages and configured to process write operations of a plurality of data words addressed to a given segment of the memory bank. The device also comprises a cache memory comprising Y number of entries, the cache memory associated with the given segment of the memory bank, and wherein the Y number of entries is based on the M, the N and the prescribed word error rate, E, to prevent overflow of the cache memory.