Dynamic Reference Cell Selection for MRAM Self-Testing
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Solution Overview
Problem
Conventional self-testing methods for MRAM memory in AI chips require redundant cells and fixed reference cells, leading to increased chip size and inefficiencies, especially in low power and high performance AI chips for mobile devices, where self-testing is time-consuming and cannot be altered post-fabrication.
Innovation Solution
An integrated circuit with an AI logic and embedded MRAM memory allows external processors to dynamically select and program reference units, updating them based on error rates to maintain acceptable performance, enabling self-testing and reusing reference cells at the chip packaging level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant reference cells are used for self-testing in MRAM memory, then memory reliability is improved, but chip size increases
Solution Approach 1:
The patent implements dynamic reference cell selection where the external processor can programmatically choose different reference cells based on error rates and performance requirements. This dynamic approach replaces the static, fixed allocation of reference cells, allowing the system to use minimal reference cells while maintaining reliability through adaptive selection and reuse.
Solution Approach 2:
The system changes the operational parameters of reference cells by allowing external reprogramming and reconfiguration. Reference cells can be switched between active and inactive states, and their selection is based on varying parameters such as error rates, performance thresholds, and application requirements, enabling the same physical cells to serve multiple functions across different operational contexts.
2Ease of manufacture
If fixed reference cells are used in conventional BIST/R methods, then manufacturing simplicity is improved, but adaptability deteriorates
Solution Approach 1:
The patent makes reference cells universal by enabling them to serve multiple functions: initial self-testing, ongoing error detection, and adaptive reconfiguration. The external processor can programmatically assign different reference cells to different storage cell groups based on performance needs, allowing the same reference cell infrastructure to adapt to varying memory quality conditions and application requirements without requiring dedicated reference cells for each scenario.
Solution Approach 2:
The system transitions from static reference cell assignment to dynamic, externally-controlled selection. The external processor can modify reference cell configurations and selections based on runtime conditions, enabling the memory system to adapt to manufacturing variations, wear, and changing performance requirements while maintaining a simple physical architecture.
3Productivity
If wafer-level self-testing is performed, then manufacturing efficiency is improved, but testing completeness deteriorates
Solution Approach 1:
The patent implements preliminary self-testing capability that can be executed at wafer level before packaging, allowing early detection of reference cell defects. This preliminary action enables manufacturers to identify and account for bad reference cells before final chip assembly, improving both manufacturing efficiency by filtering out defective units early and testing completeness by establishing a baseline for later adaptive selection algorithms.
Solution Approach 2:
The system incorporates feedback mechanisms where error rates from initial testing inform the external processor's selection of reference cells. The feedback loop allows the system to learn from initial test results and continuously optimize reference cell selection, improving testing completeness over time while maintaining manufacturing efficiency through automated, processor-driven adaptation.
4Loss of time
If reference cells are programmed at factory test stage, then initialization speed is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements dynamic reprogramming capability where the external processor can update reference cell contents and configurations after fabrication. This allows the system to maintain fast initialization through pre-programmed reference cells while adding flexibility by enabling runtime modifications, adaptive reconfiguration, and replacement of reference cell data based on performance monitoring and error analysis.
Solution Approach 2:
The system performs preliminary programming of reference cells at factory test stage to enable fast initialization, while simultaneously establishing the infrastructure for later updates. The external processor can subsequently modify reference cell contents as needed, combining the speed benefit of pre-programming with the flexibility of adaptive reconfiguration throughout the product lifecycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip size, allows for efficient self-testing, and reuses reference cells, improving memory utilization and reducing waste, while maintaining acceptable error rates for AI applications, even in mobile devices.
Implementation Method 1
an MRAM memory and includes multiple storage cells and multiple reference units
Implementation Method 2
the resistances of the storage cells will be measured and compared to those of the reference cells to decide whether a '1' or '0' is stored in each of the storage cells correctly
Data Source
AI summary
An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.