Dynamic Reference Equalization in Receiver Slicers for ISI Jitter

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Solution Overview

Problem

High-speed digital communications systems face bit errors due to inter-symbol interference and jitter, which existing decision feedback equalization (DFE) methods struggle to fully mitigate, especially in high-bandwidth environments.

Innovation Solution

A dual-mode receiver circuit that dynamically adjusts a reference voltage based on previously received logic values in one mode and provides a static reference voltage in another mode, allowing for adaptive compensation of incoming signals to reduce bit errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a static reference voltage is used in the receiver circuit, then the circuit operation is simple and stable, but the receiver cannot compensate for inter-symbol interference and jitter, leading to bit errors in high-speed communications

Engineering Contradiction:
Improvebit error rateVSAvoidreference voltage generation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The reference voltage generator is designed to operate in two modes: static mode for normal operation and dynamic mode for compensation. The dynamic mode adjusts the reference voltage based on previously received data values, enabling the system to adapt to inter-symbol interference and jitter conditions while maintaining simplicity through mode switching.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The reference voltage parameter is changed dynamically based on the received data history. When in dynamic mode, the reference voltage is adjusted according to the values of previously received signals, allowing the receiver to compensate for signal degradation without requiring a completely complex reconfiguration of the entire system.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If a dynamic reference voltage is generated based on previous data values, then inter-symbol interference and jitter are compensated, but the reference voltage path becomes complex and requires separate feedback mechanisms

Engineering Contradiction:
Improvesignal sampling accuracyVSAvoidreference voltage path complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The receiver circuit is segmented into separate functional paths: a data path for receiving and processing signal values, and a reference voltage path for generating and adjusting the reference voltage. This segmentation allows the reference voltage to be independently adjusted based on data history without complicating the main signal processing path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reference voltage acts as an intermediary element that mediates between the raw received signals and the decision-making process. By adjusting the reference voltage based on historical data, the system indirectly compensates for inter-symbol interference and jitter without requiring direct complex processing of the signal path.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the reference voltage is adjusted frequently based on feedback, then compensation for signal degradation is improved, but the switching between static and dynamic modes adds operational complexity

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidmode switching complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The system employs periodic action by switching between static and dynamic modes based on operational requirements. The dynamic mode is activated when compensation is needed (based on detected signal conditions), and the static mode is used for normal operation, creating a rhythmic pattern of adjustment that balances accuracy with operational simplicity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8634500B2Direct feedback equalization with dynamic referencing
Publication Date: 2014.01.21 ORACLE INT CORP
  • US8634500B2 patent drawing
  • US8634500B2 patent drawing
  • US8634500B2 patent drawing

AI summary

A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.