Dynamic Reference Scheme for STT-MRAM Read Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current sensing schemes for STT-MRAMs face challenges in achieving low bit error rates (BER) at low voltages and are energy-inefficient, while voltage sensing methods are less robust and consume more energy due to the need for multiple read steps and destructive operations.
Innovation Solution
A dynamic reference voltage scheme that generates different reference voltages based on the resistance state of the bitline, using a reference generator circuit that adjusts the reference voltage dynamically to improve sensing margin and reduce energy consumption by eliminating the need for multi-stage sensing and destructive reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current sensing schemes are used for STT-MRAMs, then bit error rate is reduced, but energy consumption increases and voltage scaling is prohibited
Solution Approach 1:
The patent applies dynamics by making the reference voltage dynamic rather than fixed. The reference voltage changes based on the resistance state of the accessed memory cell, allowing the sensing circuit to adapt to different operating conditions. This dynamic adjustment enables the circuit to achieve low BER at lower voltages without the energy penalties of current sensing.
Solution Approach 2:
The patent changes the parameter of reference voltage to resolve the contradiction. By adjusting the reference voltage level according to the bitline resistance state (high or low resistance), the sensing margin is optimized for each state. This parameter change allows voltage scaling while maintaining acceptable BER performance.
2Use of energy by moving object
If conventional voltage sensing is used, then energy consumption is reduced, but bit error rate increases
Solution Approach 1:
The patent transforms conventional static voltage sensing into a dynamic scheme where the reference voltage adapts to the memory cell state. This dynamic adjustment significantly improves the BER performance while maintaining the lower energy consumption characteristics of voltage sensing, as the sensing operation remains single-stage and non-destructive.
Solution Approach 2:
The patent implements feedback by using the detected resistance state of the memory cell to adjust the reference voltage level. The sensing circuit detects whether the cell is in high or low resistance state and accordingly selects the appropriate reference voltage, creating a feedback loop that optimizes the sensing margin and reduces BER.
3Measurement precision
If dual reference scheme is used, then sensing margin is improved, but device complexity increases
Solution Approach 1:
The patent simplifies the dual reference concept by making the reference voltage dynamic rather than maintaining two separate fixed reference circuits. The single dynamic reference voltage replaces the need for complex dual reference generation and selection logic, reducing device complexity while achieving similar or better sensing margin improvement.
Data Source
AI summary
A method of providing a reference voltage for reading of a resistive memory array, and a read circuit for reading of a resistive memory array. The method comprises the steps of generating a first reference voltage when a bitline of the resistive memory array is in a first resistance state, and generating a second reference voltage when the bitline is in a second resistance state; wherein the first reference voltage is different from the first reference voltage and the first resistance state is different from the second resistance state.