Dynamic Refresh Period Control for Memory Data Reliability

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Solution Overview

Problem

Semiconductor memories, particularly volatile ones like DRAM, face challenges in maintaining data reliability due to increased temperature, which requires more frequent refresh operations, leading to higher power consumption and reduced memory life.

Innovation Solution

A memory system with a peripheral circuit that includes a temperature sensing circuit, a control logic circuit, and a refresh control circuit. The temperature sensing circuit generates a temperature signal, which the control logic circuit uses, in conjunction with a mapping table, to determine a target refresh period. The refresh control circuit then adjusts the refresh period accordingly to maintain data reliability while minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh frequency is increased to maintain data reliability at higher temperatures, then data reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The refresh period is made dynamic by adjusting it according to temperature conditions. The circuit selectively applies different refresh periods (first refresh period at higher temperatures, second refresh period at lower temperatures) based on temperature sensing, allowing the system to adapt refresh frequency to actual thermal conditions rather than using a fixed conservative value.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The refresh period parameter is changed based on temperature conditions. The control circuit modifies the refresh period from a first value to a second value according to the sensed temperature, enabling the system to optimize between data reliability and power consumption by adjusting this critical timing parameter dynamically.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If refresh frequency is increased to prevent data loss, then data reliability is improved, but memory useful life decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoidmemory useful life
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The refresh operation frequency is made dynamic through temperature-based control. The circuit adjusts between different refresh periods based on sensed temperature, reducing unnecessary frequent refresh operations at lower temperatures and thereby decreasing wear on memory cells while maintaining data reliability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory system performs self-monitoring of temperature conditions and autonomously adjusts its refresh strategy accordingly. The temperature sensing circuit and control logic work together to automatically optimize refresh operations without external intervention, balancing reliability requirements with component longevity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250078900A1Memory and operating method thereof, memory system and electronic device
Publication Date: 2025.03.06 YANGTZE MEMORY TECH CO LTD
  • US20250078900A1 patent drawing
  • US20250078900A1 patent drawing
  • US20250078900A1 patent drawing

AI summary

Implementations of the present disclosure disclose a memory and an operating method thereof, a memory system, and an electronic device. The memory includes a memory cell array and a peripheral circuit coupled with the memory cell array. The peripheral circuit includes: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table, wherein the mapping table includes a plurality of preset temperature signals and a plurality of preset refresh periods in a one-to-one correspondence; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period, wherein the refresh signal is configured to indicate performing a refresh operation on the memory cell array.