Dynamic Refresh Modes for Semiconductor Memory Data Integrity
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data integrity due to information decay over time, particularly when frequently accessed rows accelerate the decay of nearby rows, requiring dynamic refresh modes to prevent data loss.
Innovation Solution
The implementation of a refresh control circuit that dynamically switches between auto-refresh and targeted refresh operations based on the location of aggressor rows within the memory array, allowing for simultaneous or sequential refresh of victim rows to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If auto-refresh operations are performed on all rows sequentially, then data integrity is maintained across the entire memory array, but the refresh time consumption increases and productivity decreases
Solution Approach 1:
The patent applies local quality by shifting from uniform auto-refresh operations on all rows to targeted refresh operations on specific victim rows identified as needing refresh. The refresh control circuit dynamically determines which rows require refresh based on aggressor row locations, applying refresh operations locally only where needed rather than globally across the entire memory array, thereby reducing overall refresh time while maintaining data integrity.
2Loss of time
If targeted refresh operations are performed on victim rows, then refresh time is reduced, but data integrity may be compromised if victim rows are not identified and refreshed timely
Solution Approach 1:
The patent implements feedback through the refresh control circuit that continuously monitors memory access patterns, identifies aggressor rows, and dynamically determines victim rows requiring refresh. This feedback mechanism ensures that targeted refresh operations are applied to the correct rows at the appropriate times, maintaining data integrity while optimizing refresh time by avoiding unnecessary refresh operations on rows that do not require them.
Solution Approach 2:
The patent applies preliminary action by proactively identifying victim rows before data loss occurs. The refresh control circuit monitors aggressor row activities and predicts which neighboring rows will be affected, performing refresh operations on these victim rows in advance before the decay becomes critical, thereby preventing data integrity issues while minimizing refresh time.
3Productivity
If multiple victim rows are refreshed simultaneously, then productivity increases, but device complexity increases due to coordination requirements
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple banks and further segmenting refresh operations into independent groups of victim rows. The refresh control circuit can simultaneously initiate refresh operations on multiple segmented groups without requiring complex coordination between them, as each segment operates independently. This segmentation approach enables parallel refresh operations that improve productivity while keeping the control logic relatively simple.
Data Source
AI summary
Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.