DRAM Refresh Timing Control for Power and Bandwidth Optimization
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Solution Overview
Problem
Dynamic random access memory (DRAM) requires continuous refreshing due to leakage currents, leading to increased bandwidth and latency issues as DRAM densities grow, and existing static refresh settings fail to adapt to varying conditions such as temperature and process variations, potentially violating power and thermal constraints.
Innovation Solution
Implementing a dynamic adjustment of refresh timing based on monitored data error rates, allowing the memory controller to adjust the frequency of refresh commands and activate alternative error handling mechanisms, such as modifying the refresh rate or activating ECC error handling, to maintain data integrity while optimizing power and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If static refresh settings are used, then device complexity is reduced, but adaptability to varying conditions such as temperature and process variations deteriorates
Solution Approach 1:
The patent implements dynamic refresh timing adjustment where the memory controller monitors data error rates and automatically modifies refresh intervals based on real-time conditions. This transitions from static to dynamic operation, allowing the system to adapt to temperature variations, process variations, and DRAM cell failures without manual intervention, thereby resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The patent establishes a feedback mechanism where the memory controller continuously monitors data error rates from DRAM operations and uses this information to adjust refresh timing parameters. This closed-loop control enables the system to respond to changing conditions and maintain optimal performance while managing the complexity through automated decision-making.
2Reliability
If refresh rate is increased to maintain data integrity, then reliability improves, but productivity deteriorates due to increased bandwidth consumption and latency
Solution Approach 1:
The patent dynamically changes the refresh rate parameter based on monitored data error rates. When error rates indicate deteriorating data integrity, the system increases the refresh rate to maintain reliability. Conversely, when data integrity is stable, the system reduces the refresh rate to improve bandwidth availability and reduce latency, thus resolving the contradiction through adaptive parameter adjustment.
Solution Approach 2:
The patent implements dynamic refresh rate adjustment that responds to real-time data error conditions. This dynamic approach allows the system to optimize between reliability and productivity by increasing refresh rates only when necessary to maintain data integrity, rather than maintaining a constantly high refresh rate that would waste bandwidth and increase latency.
3Reliability
If refresh rate is increased to compensate for DRAM cell failures, then reliability improves, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the refresh rate parameter in response to monitored data error rates and DRAM cell failure conditions. When reliability threats are detected, the system increases the refresh rate to maintain data integrity. When conditions are stable, the system reduces the refresh rate to minimize power consumption, thereby resolving the contradiction between reliability and energy usage through adaptive control.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller monitors data error rates and uses this information to automatically adjust refresh timing parameters. This closed-loop control ensures that power is consumed only when necessary to maintain data integrity, avoiding wasted energy from excessive refreshing while still providing adequate protection against DRAM cell failures.
Data Source
AI summary
Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate.