Dynamic Register Allocation in Binary Translation

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Solution Overview

Problem

Binary translation processes face limitations in register allocation, particularly when translating source code to target code for different processor architectures, as static 1:1 allocation of registers is not always possible, leading to overhead from register saving and restoring operations.

Innovation Solution

The implementation of dynamic register allocation schemes with optimized source-to-target register mappings, using weight values to prioritize register selection and minimize overhead through tie code generation for connecting sequentially executed code fragments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If static 1:1 allocation of registers is used, then register mapping is simple, but overhead from register saving and restoring operations increases

Engineering Contradiction:
Improveregister mapping complexityVSAvoidoverhead from register saving and restoring
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements dynamic register allocation where the register mapping between source and target architectures is not fixed but adapts based on the specific code fragment being translated. The system determines optimal register mappings dynamically during binary translation, allowing different mappings for different code fragments rather than using a static 1:1 allocation scheme throughout.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the register allocation parameters dynamically based on the translation context. By adjusting which source registers map to which target registers depending on the specific code fragment, the system optimizes performance for each fragment while minimizing the need for save/restore operations.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If dynamic register allocation is used, then overhead from register saving and restoring operations is reduced, but register allocation complexity increases

Engineering Contradiction:
Improveoverhead from register saving and restoringVSAvoidregister allocation complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides the translation process into segments where each code fragment is translated with its own optimized register allocation. By segmenting the binary code into translatable units and applying dynamic register allocation at the fragment level, the system reduces save/restore overhead while managing complexity through localized optimization rather than global complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary analysis to determine optimal register mappings before translating each code fragment. By pre-determining the best register allocation for upcoming code fragments, the system can minimize save/restore operations while managing complexity through advance planning rather than reactive complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11748078B1Generating tie code fragments for binary translation
Publication Date: 2023.09.05 PARALLELS INT GMBH
  • US11748078B1 patent drawing
  • US11748078B1 patent drawing
  • US11748078B1 patent drawing

AI summary

Systems and methods for binary translation of executable code. An example binary translation method comprises: decoding a current source code fragment compatible with a source instruction set architecture (ISA); identifying a first source register referenced by the current source code fragment; determining that the first source register is not referenced by a register mapping table, wherein the register mapping table comprises a plurality of entries, each entry specifying a source register, a target register, and a weight value; identifying, among the plurality of mapping table entries, a mapping table entry comprising a highest weight value, wherein the identified mapping table entry specifies a second source register and a second target register; replacing, in the identified mapping table entry, an identifier of the second source register with an identifier of the first source register; and translating, using the mapping table entry, the current source code fragment into a target code fragment, wherein the target code fragment is compatible with a target ISA.