Dynamic Register Assignment for Serial Data Frame Error Detection
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Solution Overview
Problem
In automation and drive technology, serial data frames can be difficult to evaluate reliably due to errors that occur when data storage fails, leading to the same measured value being output continuously, especially during periods of no change, which can be challenging to detect.
Innovation Solution
A device comprising a serial/parallel converter unit, an evaluation unit, and multiple data registers that cyclically change the assignment of data blocks to registers, allowing the evaluation unit to control storage based on the contents of the serial data frames, reducing residual error probability and data volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored continuously in the same data register, then data transmission simplicity is maintained, but error detection capability deteriorates when the measured value does not change
Solution Approach 1:
The patent applies dynamics by making the data register assignment changeable rather than fixed. The evaluation unit dynamically assigns incoming data blocks to different data registers based on a changing assignment pattern, allowing the system to adapt its storage configuration over time. This dynamic reassignment enables error detection while maintaining operational simplicity.
Solution Approach 2:
The patent implements periodic action through cyclic changing of the data register assignment. The evaluation unit periodically changes which data register receives which data block, creating a repeating pattern of assignment changes. This periodic reassignment ensures that if a data register becomes defective, the system will eventually detect the error when the assignment pattern changes and attempts to store data in a different register.
2Reliability
If redundant measures are implemented for functional safety, then safety integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by making the evaluation unit perform multiple functions. The evaluation unit not only evaluates the contents of serial data frames but also controls the assignment of data blocks to data registers and changes the assignment pattern. This multi-functionality provides redundant safety measures without requiring separate dedicated components, thereby limiting the increase in device complexity.
3Productivity
If data blocks are transmitted within a single data frame, then transmission efficiency is maintained, but error detection capability deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the data transmission into separate data frames, each containing a single data block from a set of related data blocks. Instead of transmitting all data blocks in one frame, the system segments them across multiple frames and uses changing assignments to detect errors, thereby maintaining transmission efficiency while improving error detection.
Data Source
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AI summary
The present invention relates to a device and a method for processing serial data frames. The device comprises a serial/parallel converter unit (42, 142), an evaluation unit (48, 148) and at least two data registers (44, 45, 144, 145, 146, 160), wherein: • serial data frames (F, F1-F9) are supplied to the serial/parallel converter unit (42, 142) and serial data blocks (A, B, P1, P2A, P2B, P2C) contained in the serial data frames (F, F1-F9) are convertible by the serial/parallel converter unit (42, 142) into parallel data blocks (A, B, P1, P2A, P2B, P2C) and output to the data registers (44, 45, 144, 145, 146, 160), • the parallel data blocks (A, B, P1, P2A, P2B, P2C) can be stored in the data registers (44, 45, 144, 145, 146, 160) and output from these to a processing unit (50, 150) for further processing and • the serial data frames (F,F1-F9) are supplied and the storage of the parallel data blocks (A, B, P1, P2A, P2B, P2C) into the data registers (44, 45, 144, 145, 146, 160) can be controlled by the evaluation unit (48, 148) depending on the contents of the serial data frames (F, F1-F9). According to the invention, n data registers (44, 45, 144, 145, 146) are provided for storing n related data blocks (A, B, P2A, P2B, P2C), and the assignment of the related n data blocks (A, B, P2A, P2B, P2C) to the n data registers (44, 45, 144, 145, 146) in which they are stored is modifiable by the evaluation unit (48, 148), where n is a natural number greater than or equal to two.