Dynamic Register Circuit With Keeper for Short Setup and Hold Times
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Solution Overview
Problem
Dynamic logic circuits often exhibit long setup and hold times, requiring buffers that consume valuable space and power, especially for clock signals at or near 50% duty cycle, and pulsed clock generators offer limited solutions.
Innovation Solution
A fast dynamic register circuit is designed with first and second precharge circuits, a full keeper circuit, and an output circuit that precharge and discharge nodes based on clock and data signals, minimizing setup and hold times without the need for buffers or pulsed clock generators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If buffers are used to hold data for the requisite amount of time, then the hold time is ensured, but space and power are consumed
Solution Approach 1:
The patent extracts the data holding function from separate buffer circuits and integrates it into the dynamic register circuit itself through the keeper circuit and precharge node configuration. The keeper circuit maintains the state of the second precharge node without requiring external buffers, thereby eliminating the space and power overhead of separate buffer components while ensuring proper hold time.
Solution Approach 2:
The patent combines multiple functions (data registration, hold time enforcement, and state maintenance) into a single integrated dynamic register circuit. The first and second precharge circuits, keeper circuit, and output circuit work together as a unified structure that simultaneously achieves data latching and hold time requirements without needing separate buffer stages.
2Duration of action of stationary object
If buffers are used to hold data, then proper operation is ensured, but power consumption increases
Solution Approach 1:
The patent removes the need for power-hungry buffer circuits by extracting the data holding capability and embedding it within the dynamic register's internal structure. The keeper circuit and precharge node arrangement provide the necessary hold time function without the continuous power consumption associated with traditional buffer circuits.
Solution Approach 2:
The dynamic register circuit serves its own data holding needs through its internal keeper circuit and precharge mechanism. The first precharge node and second precharge node work together with the keeper circuit to maintain data state without requiring external power-consuming buffer assistance, making the circuit self-sufficient for hold time requirements.
3Reliability
If dynamic logic circuits use traditional designs, then operation is reliable, but setup and hold times are long
Solution Approach 1:
The patent segments the dynamic register circuit into distinct functional blocks: a first precharge circuit for initial data capture, a second precharge circuit for state maintenance, a keeper circuit for hold time enforcement, and an output circuit. This segmentation allows each component to be optimized for its specific function, reducing overall setup and hold times while maintaining operational reliability through coordinated operation of the segments.
Solution Approach 2:
The patent implements preliminary precharging of the first and second precharge nodes before the clock edge arrives. The first precharge circuit precharges the first precharge node high while the clock is low, and the second precharge circuit precharges the second precharge node high while the clock is low. This preliminary action ensures that the nodes are ready to quickly respond to the clock edge, minimizing setup time while maintaining reliable operation.
Data Source
AI summary
A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.