Dynamic Register Leakage Compensation for Stable Data Storage
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Solution Overview
Problem
Dynamic registers suffer from significant dynamic leakage currents, leading to data loss and reduced data security and accuracy.
Innovation Solution
A leakage compensation dynamic register is introduced, incorporating an analog switch unit, data latch unit, output drive unit, and leakage compensation unit to mitigate leakage currents by feeding them back to the storage node, enhancing data stability and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dynamic register uses parasitic capacitances of transistors to temporarily store data, then data storage function is achieved, but dynamic leakage current is generated causing data loss
Solution Approach 1:
The patent implements a leakage compensation unit that detects dynamic leakage current at the storage node and feeds back a compensating current to offset the leakage. This feedback mechanism continuously monitors and corrects the leakage effect, maintaining data stability without requiring complete structural redesign of the dynamic register.
Solution Approach 2:
The patent introduces a leakage compensation unit as an intermediary component between the storage node and ground. This unit acts as a mediator that captures the leakage current and redirects it through compensation transistors to replenish the storage node, preventing direct data loss while maintaining the original dynamic register operation.
2Reliability
If leakage compensation unit is added to the dynamic register, then data storage stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the leakage compensation function with the existing dynamic register structure by sharing common components such as the storage node, clock signal lines, and power supply connections. The compensation transistors are integrated into the existing circuit layout, reducing the need for completely separate compensation circuits and minimizing overall complexity increase.
Solution Approach 2:
The leakage compensation unit is designed to work universally with standard dynamic register configurations, using the same clock signals and power supplies already present in the system. The compensation transistors can be configured to work with different storage node arrangements, making the solution adaptable to various dynamic register designs without requiring custom compensation circuits for each case.
Data Source
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AI summary
The invention provides a leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal. The invention can effectively compensate for a dynamic leakage current of the node, thereby improving data security and accuracy.