Dynamic Repeater Circuit With Keeper Feedback for Long Interconnects
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Solution Overview
Problem
As integrated circuits (ICs) operate at higher speeds with decreasing voltages, long signal interconnects on ICs face resistance and capacitance issues, leading to signal transition delays and potential circuit damage due to crowbar currents, which repeater circuits aim to mitigate but can still be susceptible to RC sensitivity and power consumption problems.
Innovation Solution
A repeater circuit design featuring an input stage, intermediate stage, output stage, and a keeper circuit with a feedback path, where only one intermediate and output circuit chain is activated per logic signal transition, and the keeper maintains the output signal after deactivation, reducing power consumption and sensitivity to resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If repeater circuits are placed along long signal interconnects to overcome resistance and capacitance effects, then signal transition speed at the receiver is improved, but power consumption increases and the circuit becomes more complex
Solution Approach 1:
The patent applies dynamic operation to the repeater circuit by using dynamic logic gates (dynamic NAND gates and dynamic inverters) instead of static logic gates. The circuit operates in precharge and evaluate phases, allowing signals to be transmitted with reduced power consumption while maintaining fast transition speeds. The dynamic nature enables the circuit to switch states efficiently without continuous power dissipation.
Solution Approach 2:
The repeater circuit employs periodic precharging of internal nodes during the precharge phase, followed by evaluation during the evaluate phase. This periodic action allows the circuit to reset and prepare for the next signal transition, reducing cumulative power consumption while maintaining the ability to drive long interconnects effectively.
2Speed
If repeater circuits are placed along long signal interconnects to overcome resistance and capacitance effects, then signal transition speed at the receiver is improved, but the circuit complexity increases
Solution Approach 1:
The repeater circuit is segmented into distinct functional blocks: a dynamic NAND gate section, a dynamic inverter section, and a feedback path with additional inverters. This segmentation allows each section to perform a specific function efficiently, reducing overall circuit complexity while maintaining the ability to drive long interconnects with fast transition times.
Solution Approach 2:
The circuit incorporates a feedback path that monitors the output and feeds it back to control the switching of transistors in the main signal path. This feedback mechanism automatically adjusts the circuit operation based on the signal state, simplifying control logic while ensuring proper signal transmission across long interconnects.
3Device complexity
If simple repeater circuits like inverters or buffers are used, then the circuit complexity is reduced, but sensitivity to resistance and capacitance in long interconnects increases
Solution Approach 1:
The use of dynamic logic gates provides stronger drive capability compared to static gates of the same size. The dynamic operation allows the circuit to overcome RC effects in long interconnects more effectively, improving reliability without significantly increasing complexity. The precharge phase ensures nodes are properly initialized, and the evaluate phase provides strong switching action.
Solution Approach 2:
The repeater circuit combines different logic gate types (dynamic NAND gates and dynamic inverters) in a composite structure. This composite design leverages the advantages of each gate type: the NAND gate provides logic functionality with reduced transistor count, while the inverters provide signal restoration and drive strength, together achieving low sensitivity to RC effects.
4Power
If output devices drive the output for the entire cycle, then the signal strength is maintained, but power consumption increases
Solution Approach 1:
Output devices are activated periodically during the evaluate phase rather than continuously. During the precharge phase, output devices are turned off, and during the evaluate phase, they are activated to drive the output signal. This periodic operation maintains signal strength when needed while minimizing power consumption during idle periods.
Solution Approach 2:
The dynamic logic structure ensures that useful action (signal driving) occurs continuously during the evaluate phase without interruption, maintaining strong output signals. The precharge phase prepares the circuit for the next evaluation, ensuring continuity of operation while allowing power savings during the transition periods.
Data Source
AI summary
A repeater circuit. The repeater circuit includes two input circuits, two intermediate circuits, and two output circuits. Responsive to a transition of an input signal from one logic level to another level, one of the input circuits is activated. The corresponding intermediate circuit is activated corresponding to activation one of the input circuits, and in turn, the corresponding output circuit is activated, which then drives an output signal on an output node. After a delay, a feedback signal conveyed via a feedback path deactivates the corresponding intermediate circuit and the corresponding output circuit. After deactivation of the corresponding output circuit, a keeper circuit continues to provide the output signal on the output node. The other one of the two input circuits inhibits activation of the other one of the intermediate circuit responsive to the transition, which results in the other output circuit also being inhibited from activation.