Dynamic Repetitive Load Representation in Circuit Simulation
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Solution Overview
Problem
Current simulation methods for integrated circuits with high component density and hierarchical data structures face challenges in efficiently predicting system-wide behaviors due to exponentially increasing matrix sizes and inefficient communication of signal changes across hierarchical structures, leading to long simulation cycles and high computational resource usage.
Innovation Solution
A system that dynamically represents repetitive loads by identifying driver circuits, creating branch node drivers, and using a port connectivity interface to efficiently communicate changes, thereby reducing memory usage and improving simulation performance by aggregating input port loads and optimizing matrix computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional simulation methods are used for high component density circuits, then simulation accuracy is maintained, but simulation time and computational resource usage increase exponentially
Solution Approach 1:
The patent merges multiple identical or similar circuit components into a single representative component model. Instead of simulating each component individually, the system creates a consolidated representation that captures the collective behavior of grouped components, thereby reducing the overall system complexity and simulation time while preserving accuracy.
Solution Approach 2:
The patent develops a universal component model that can represent multiple different circuit components through parameterization. This universal model can be configured to represent various component types and can handle different operating conditions, reducing the need for separate detailed models for each component type and enabling more efficient simulation.
2Measurement precision
If detailed hierarchical circuit models are used, then system-wide behavior prediction accuracy is improved, but memory usage and computational complexity increase
Solution Approach 1:
The patent segments the hierarchical circuit model into distinct levels and layers, allowing selective detailed modeling at critical levels while using aggregated representations at higher levels. This segmentation enables the system to maintain accuracy where needed while reducing overall computational complexity by avoiding unnecessary detail throughout the entire hierarchy.
Solution Approach 2:
The patent implements dynamic model detail adjustment based on simulation needs. The system can adaptively refine or coarsen the level of detail in different parts of the hierarchical model during simulation, allowing computational resources to be focused on critical regions while using simplified representations elsewhere, thereby managing complexity while maintaining prediction accuracy.
3Reliability
If signal changes are communicated across hierarchical structures, then simulation completeness is maintained, but communication overhead and simulation cycles increase
Solution Approach 1:
The patent extracts and separates the signal communication mechanism from the detailed hierarchical structure. By creating an independent communication interface that operates at the boundary of hierarchical levels, the system can propagate signal changes without requiring traversal through all intermediate levels, thereby maintaining simulation completeness while reducing communication overhead and improving efficiency.
Data Source
AI summary
A system for dynamically representing repetitive loads of a circuit during simulation includes a simulator module having one or more computer programs for 1) identifying one or more driver circuits for driving a plurality of repetitive receiver circuits, where each driver circuit has an output port and each repetitive receiver circuit has an input port, 2) creating a branch node driver for connecting the input ports of the plurality of repetitive receiver circuits and the output ports of the one or more driver circuits, 3) creating a shared load for representing aggregated input port loads of the plurality of receiver circuits having a substantially same isomorphic behavior, 4) creating a port connectivity interface for communicating changes of signal conditions between the output ports of the one or more driver circuits and the corresponding input ports of the plurality of repetitive receiver circuits, and 5) simulating the one or more driver circuits and the plurality of repetitive receiver circuits in accordance with the branch node driver, the shared load and the port connectivity interface.