Dynamic Reset Latency Control for Digital Logic Power Optimization
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Solution Overview
Problem
Digital logic systems face a tradeoff between reset latency and power usage, with fixed latency designs often inefficiently using power and lacking flexibility in managing latency based on voltage requirements.
Innovation Solution
Implementing a dynamic reset latency system that adjusts latency based on the required voltage, using a reset synchronizer to control the reset and clock networks, allowing for programmable and predictable latency management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed latency is used for all resets, then the system design is simple, but power is wasted during resets that don't require high latency
Solution Approach 1:
The patent applies dynamics by making the reset latency adjustable rather than fixed. The system can dynamically change the number of clock cycles the reset synchronizer runs based on the specific reset scenario, allowing the system to adapt between low-latency and high-latency reset modes as needed, thereby reducing unnecessary power consumption while maintaining simplicity in the core design
Solution Approach 2:
The patent changes the parameter of reset latency from a fixed value to a variable parameter that can be adjusted based on system state. By modifying the latency parameter dynamically, the system optimizes power consumption during reset operations without compromising the simplicity of the underlying reset mechanism
2Adaptability or versatility
If a higher voltage is used for reset, then the reset can handle more complex scenarios, but the latency increases
Solution Approach 1:
The system dynamically adjusts the reset latency based on the voltage level and complexity of the reset scenario. When high voltage is applied for complex resets, the system increases latency to accommodate the additional synchronization cycles needed. When lower voltage is sufficient, the system uses reduced latency, creating an adaptive balance between reset capability and time
3Loss of time
If a lower voltage is used for reset, then the latency is reduced, but the reset may not handle complex error conditions
Solution Approach 1:
The system dynamically selects the appropriate voltage level and corresponding latency based on the detected reset condition. For simple reset scenarios, the system uses lower voltage with reduced latency. For complex error conditions, the system automatically increases voltage and adjusts latency accordingly, maintaining both speed and capability
4Adaptability or versatility
If the reset latency is made variable, then the system becomes more flexible, but the control complexity increases
Solution Approach 1:
The reset synchronizer is designed to self-regulate its own latency based on system conditions. The control logic automatically determines the appropriate number of clock cycles without requiring external intervention or complex control mechanisms, maintaining flexibility while minimizing added complexity through self-service operation
Data Source
AI summary
A method of resetting a number of functional components in a computing device includes determining a number of cycles required to reset the functional components based on a predetermined voltage controlling a reset synchronizer to run for the determined number of cycles wherein the reset synchronizer controls a reset network connected to the functional components, and wherein the determined number of cycles at a first voltage is different than a determined number of cycles at a second voltage.