Dynamic Root Clock Frequency Adjustment for Logic Verification
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Solution Overview
Problem
The existing IC chip design verification process is time-consuming due to a fixed root clock frequency determined by the longest signal propagation path, which does not account for signal paths with unchanged inputs, leading to suboptimal emulation speed.
Innovation Solution
A method and apparatus to dynamically adjust the root clock frequency by identifying and excluding signal paths with unchanged inputs, determining the root clock frequency based on the longest propagation delay of paths with changing signals, using check logic to assess signal states and logic devices along the paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the root clock frequency is determined by the longest signal propagation path, then the signal integrity is ensured, but the emulation time is excessively long
Solution Approach 1:
The patent implements dynamic adjustment of the root clock frequency during the emulation process. The clock frequency is initially set based on the longest signal path, then progressively increased as verification proceeds. This dynamic adaptation allows the system to maintain signal integrity when needed while reducing emulation time when the full clock frequency is not required, directly resolving the contradiction between reliability and time loss.
Solution Approach 2:
The patent changes the root clock frequency parameter during emulation based on verification progress and signal path analysis. By adjusting this critical parameter dynamically rather than keeping it fixed, the system can optimize between maintaining signal integrity (lower frequency) and reducing emulation time (higher frequency), thus resolving the technical contradiction.
2Productivity
If the root clock frequency is increased to reduce emulation time, then the productivity is improved, but the signal propagation delay may cause verification errors
Solution Approach 1:
The system dynamically adjusts the root clock frequency based on the current emulation stage and signal path conditions. Rather than using a fixed high frequency that could cause verification errors, the frequency is adapted in real-time to match the actual signal propagation requirements, thus maintaining verification accuracy while maximizing emulation speed.
Solution Approach 2:
The patent performs preliminary analysis of signal paths and their propagation delays before setting the root clock frequency. By预先 identifying critical paths and estimating their delays, the system can pre-calculate an appropriate clock frequency that ensures verification accuracy is not compromised, thereby enabling high productivity from the start without risking verification errors.
3Stability of the object's composition
If the root clock frequency is fixed at the beginning, then the system stability is maintained, but the emulation process takes excessive time
Solution Approach 1:
The patent transitions from a static, fixed root clock frequency to a dynamic, adjustable frequency scheme. The system maintains stability through controlled, incremental frequency adjustments based on verification progress and signal path analysis, rather than abrupt changes. This dynamic approach reduces emulation duration while preserving system stability through methodical adaptation.
Solution Approach 2:
The root clock frequency parameter is changed during the emulation process based on measured signal propagation characteristics and verification needs. This parameter change enables the system to reduce emulation time by operating at higher frequencies when appropriate, while maintaining stability through controlled adjustment rather than fixed operation.
4Reliability
If signal paths with unchanged inputs are included in the frequency calculation, then the worst-case scenario is covered, but the emulation speed is reduced
Solution Approach 1:
The patent segments the signal paths into different categories based on their input signal characteristics. Paths with unchanged inputs are identified and treated differently from paths with changing inputs. This segmentation allows the system to calculate clock frequency based only on relevant paths (those with changing inputs), excluding unnecessary paths that would slow down emulation, thus improving productivity while maintaining adequate coverage of actual signal variations.
Solution Approach 2:
The patent extracts and excludes signal paths with unchanged inputs from the critical path analysis used to determine the root clock frequency. By taking out these irrelevant paths from the frequency calculation, the system can operate at higher clock frequencies without compromising the verification of actual signal transitions, thereby improving emulation speed while maintaining sufficient worst-case coverage for relevant paths.
Data Source
AI summary
A method for dynamically adjusting a root clock frequency of a logic system design on an emulation system comprises: identifying a plurality of signal paths from one of a plurality of signal inputs of the logic system design to one of a plurality of signal outputs of the logic system design, each of the plurality of signal paths having a signal propagation delay; determining a state of an input signal to a target signal input in a current root clock cycle; determining a target signal path based on the state of the target signal input in the current root clock cycle and one or more logic devices along each signal path associated with the target signal input; and determining the root clock frequency based on a longest signal propagation delay of the signal propagation delays of the plurality of signal paths excluding the target signal path.