Dynamic Routing for NoC-Based DNN Accelerators
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Solution Overview
Problem
Deep neural network (DNN) accelerators with network-on-chip (NoC) architecture face challenges in efficiently managing channel congestion and power consumption due to asymmetric computing loads and unbalanced network traffic, leading to idle buffers and increased latency.
Innovation Solution
A method is introduced to dynamically select routing schemes based on compiler information, employing buffer gating control and contention-free switching when congestion is low, and adaptive routing algorithms when congestion occurs, to minimize energy consumption and avoid deadlock and livelock in NoC systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If buffer gating control and contention-free switching are used, then energy consumption is reduced, but channel congestion occurs leading to increased latency
Solution Approach 1:
The patent implements dynamic routing scheme selection that adapts to changing network conditions. The system monitors compiler information including channel bandwidths and NoC throughput to determine when to switch between first routing scheme (buffer gating control) and second routing scheme (adaptive routing), allowing the system to optimize for energy consumption under low congestion while avoiding latency penalties when congestion occurs
Solution Approach 2:
The patent changes routing parameters based on compiler information about channel bandwidths and throughput requirements. By analyzing whether bandwidth requirements meet throughput capabilities, the system selects appropriate routing schemes, effectively using parameter changes to resolve the contradiction between energy efficiency and latency performance
2Loss of time
If adaptive routing algorithm is used, then channel congestion is avoided, but energy consumption increases due to continuous buffer operation
Solution Approach 1:
The system dynamically selects between adaptive routing and buffer gating control based on real-time assessment of compiler information. When channel bandwidths indicate congestion risks, adaptive routing is activated to maintain low latency; when conditions permit, the system switches to buffer gating control to minimize energy consumption, thus dynamically balancing the latency-energy tradeoff
3Adaptability or versatility
If network-on-chip architecture is used for DNN accelerators, then design flexibility and scalability are improved, but channel congestion and unbalanced traffic increase leading to idle buffers
Solution Approach 1:
The patent employs feedback mechanisms by monitoring compiler information about channel bandwidths and NoC throughput to assess network congestion conditions. This feedback drives the selection of routing schemes, allowing the system to respond to actual traffic patterns and congestion levels, thereby reducing idle buffer energy consumption while maintaining the flexibility benefits of NoC architecture
Solution Approach 2:
The system performs self-service by autonomously selecting appropriate routing schemes based on compiler information without external intervention. The NoC-based DNN accelerator automatically assesses its own congestion conditions and adjusts routing behavior accordingly, enabling it to service its own energy optimization needs while maintaining design flexibility
Data Source
AI summary
Aspects of the present disclosure provide a method for controlling a processing device to execute an application that runs on a neural network (NN). The processing device can include a plurality of processing units that are arranged in a network-on-chip (NoC) architecture. For example, the method can include obtaining compiler information relating the application and the NoC, controlling the processing device to employ a first routing scheme to process the application when the compiler information does not meet a predefined requirement, and controlling the processing device to employ a second routing scheme to process the application when the compiler information meets the predefined requirement.