Dynamic Row Refresh Logic for Memory Devices
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Solution Overview
Problem
As memory devices become more integrated and miniaturized, they are susceptible to row hammer disturbances, where repeated access to one row can affect adjacent rows, leading to data reliability issues and increased reliance on refresh operations.
Innovation Solution
A memory device with a target row refresh logic, a weak pattern detector, and a mode register circuit that performs refresh operations based on a risk level determined by the weak pattern detector, allowing for dynamic adjustment of Rolling Accumulated ACT (RAA)-related register values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are miniaturized and highly integrated, then storage density is improved, but susceptibility to row hammer disturbance increases
Solution Approach 1:
The memory device is divided into multiple banks, with each bank independently managing its own refresh operations. The disturbance detection and refresh control logic is segmented to operate at the bank level, allowing localized response to row hammer attacks without affecting the entire memory device. This segmentation isolates the impact of miniaturization-induced vulnerability.
Solution Approach 2:
The system performs preliminary detection of weak patterns that are susceptible to row hammer attacks before actual disturbance occurs. By monitoring access patterns and identifying vulnerable rows in advance, the system can proactively apply refresh operations to prevent data loss, rather than reacting after damage has occurred.
Solution Approach 3:
The system implements a feedback mechanism where the detected risk level from weak pattern analysis directly influences the refresh operation intensity. The refresh control logic continuously monitors disturbance indicators and adjusts refresh frequency accordingly, creating a closed-loop system that adapts to real-time threat levels caused by high integration.
2Reliability
If refresh operations are increased to counter row hammer attacks, then data reliability is improved, but power consumption increases
Solution Approach 1:
The refresh operation parameters are made dynamic rather than static. The system adjusts refresh frequency and intensity based on real-time detection of weak patterns and risk levels. When row hammer attacks are detected, refresh operations are intensified; when no threats are present, refresh operations return to normal levels, optimizing the balance between reliability and power consumption.
Solution Approach 2:
The system changes operational parameters (refresh interval, refresh intensity) based on detected conditions. By monitoring weak patterns and adjusting refresh parameters dynamically, the system ensures data reliability is maintained only when necessary, rather than continuously applying maximum refresh operations, thereby reducing unnecessary power consumption.
3Reliability
If monitoring and detection mechanisms are added to identify weak patterns, then ability to counter row hammer attacks is improved, but device complexity increases
Solution Approach 1:
The detection and refresh control logic is integrated into the existing memory control structure, allowing the same hardware components to serve multiple functions. The weak pattern detector utilizes existing access pattern monitoring capabilities, and the refresh control logic leverages existing refresh mechanisms, thereby reducing the need for entirely new dedicated components and minimizing complexity increase.
Solution Approach 2:
The memory device performs self-detection and self-protection against row hammer attacks. The weak pattern detector automatically identifies vulnerable rows, and the refresh control logic autonomously determines and executes appropriate refresh operations without requiring external intervention. This self-service approach eliminates the need for complex external monitoring systems.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.