Dynamic Sampling Optimization in Hardware-Assisted Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current chip verification methodologies, particularly for System-on-a-Chip (SOC) designs, face inefficiencies due to inadequate sampling strategies, leading to prolonged verification times and compromised throughput in hardware-assisted simulation environments, as they often rely on worst-case or empirically determined sampling values, which can result in either over-sampling or under-sampling, affecting the balance between the accelerator and host computer interaction.
Innovation Solution
A system and method that employs a binary convergence algorithm to dynamically adjust sampling values based on feedback from Bus Functional Models (BFMs), using a software-readable register to count samples and maintain a DOIT flag for transaction management, allowing for optimal sampling by calculating new sampling values through the algorithm's iterative process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If worst-case or empirically determined sampling values are used, then the accelerator is protected from starvation, but the host computer interaction increases and overall throughput is compromised
Solution Approach 1:
The patent implements a feedback mechanism where the binary convergence algorithm continuously monitors the actual number of samples consumed by the accelerator and adjusts the sampling value dynamically. The algorithm uses feedback from previous sampling iterations to converge on the optimal sampling value, balancing accelerator workload with host computer interaction frequency.
Solution Approach 2:
The patent transitions from static worst-case or empirical sampling values to dynamic sampling values that adapt based on actual accelerator consumption patterns. The binary convergence algorithm dynamically adjusts the sampling value for each transaction type based on feedback from previous executions, optimizing the balance between accelerator utilization and host computer interaction.
2Ease of manufacture
If empirically determined sampling values are used, then implementation is simple, but the sampling may be suboptimal leading to extended verification time
Solution Approach 1:
The patent implements a self-service mechanism where the system automatically determines optimal sampling values through the binary convergence algorithm without requiring manual empirical tuning. The algorithm self-adjusts sampling values based on actual accelerator consumption patterns, eliminating the need for complex empirical determination while optimizing verification time.
3Reliability
If the number of samples is increased to fully exercise the design, then verification completeness improves, but the verification phase duration increases
Solution Approach 1:
The patent changes the sampling parameter dynamically based on actual accelerator consumption patterns rather than using fixed high values. The binary convergence algorithm adjusts the sampling value to the minimum necessary to fully exercise the design, eliminating unnecessary samples that extend verification duration while maintaining verification completeness.
Data Source
AI summary
Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.