Dynamic Scheduling Circuitry for Short Path Error Suppression
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Solution Overview
Problem
Existing data processing systems face issues with false positive error detection due to 'short path' errors, which can lead to incorrect detection of signal changes as errors, requiring additional buffering and analysis to suppress these errors.
Innovation Solution
Implementing dynamic scheduling circuitry that suppresses the issue of program instructions to error-detecting execution units on consecutive processing cycles, allowing for the avoidance of short path errors without the need for additional buffering by redistributing instructions to duplicate resources within the processing system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detecting circuitry is added to detect signal changes following sampling, then error detection capability is improved, but false positive detection occurs due to short path errors
Solution Approach 1:
The scheduling circuitry proactively prevents short path errors by controlling the timing of instruction issuance before the error can occur. By suppressing issuance of instructions to execution units on consecutive clock cycles, the system eliminates the condition that causes false positive error detection, rather than attempting to detect or correct the error after it occurs.
2Reliability
If buffer circuits are added to slow signal propagation, then short path errors are suppressed, but device complexity increases
Solution Approach 1:
The system uses dynamic scheduling control that adapts the issuance of instructions based on the state of execution units. The scheduling circuitry dynamically adjusts timing by suppressing instructions on consecutive cycles when needed, providing a flexible, software-controlled solution instead of fixed hardware buffering.
Solution Approach 2:
The patent replaces the mechanical/hardware solution of adding buffer circuits with a control logic solution implemented in the scheduling circuitry. Instead of physically slowing down signal propagation through additional hardware stages, the system uses scheduling decisions to prevent the error condition from occurring in the first place.
3Measurement precision
If additional analysis is performed to identify short paths requiring buffering, then error detection accuracy is improved, but processing time increases
Solution Approach 1:
The scheduling circuitry maintains separate state information for each execution unit, tracking whether each unit received an instruction on the previous clock cycle. This segmented tracking approach allows the system to quickly determine which execution units are susceptible to short path errors without performing comprehensive analysis of all possible signal paths.
Data Source
AI summary
A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.