Dynamic Scheduling Control Signaling CRC Optimization

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Solution Overview

Problem

In LTE systems, the introduction of two-stage DCI for dynamic scheduling leads to varying numbers of blind decodings and false alarm probabilities, resulting in inefficient use of control signaling resources due to fixed-length CRCs.

Innovation Solution

A method where the first and second bit blocks in a time-frequency resource set include dynamic control information, with the second bit block having a shorter or no CRC, associated with the first bit block, reducing the number of CRC check bits and improving spectrum efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed-length CRC is used in two-stage DCI, then false alarm probability is reduced, but control signaling overhead increases

Engineering Contradiction:
Improvefalse alarm probabilityVSAvoidcontrol signaling overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies different CRC lengths to different stages of DCI: the first-stage DCI uses a first CRC length (e.g., 16 bits) while the second-stage DCI uses a second CRC length (e.g., 8 bits) or no CRC. This local differentiation optimizes the balance between false alarm probability and signaling overhead for each stage's specific requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the CRC parameter (length) based on the DCI stage. The first-stage DCI employs a longer CRC to handle more blind decodings and reduce false alarms, while the second-stage DCI uses a shorter CRC or no CRC since it benefits from the association with the first stage and requires fewer blind decodings.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If same-length CRC is used for both first-stage and second-stage DCI, then error check consistency is maintained, but spectrum efficiency decreases

Engineering Contradiction:
Improveerror check consistencyVSAvoidspectrum efficiency
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

Different CRC lengths are assigned to different DCI stages based on their specific needs. The first-stage DCI uses a longer CRC for robust error checking during blind decoding, while the second-stage DCI uses a shorter CRC or no CRC, optimizing spectrum efficiency while maintaining adequate error check consistency through the association mechanism.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The CRC configuration is made dynamic and adaptive to the DCI stage. The system dynamically adjusts the CRC length based on the stage number, allowing the error check mechanism to be consistent with the specific requirements of each stage rather than applying a static uniform approach.

Inventive Principle:
Principle #15Dynamics

3Reliability

If longer CRC is used in second-stage DCI, then error detection capability is improved, but control signaling overhead increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcontrol signaling overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The first-stage DCI performs preliminary error checking with a longer CRC before the second-stage DCI is processed. This preliminary action reduces the need for extensive error detection in the second stage, allowing the second-stage DCI to use a shorter CRC or no CRC while maintaining overall reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different CRC lengths to different stages: the first-stage DCI uses a longer CRC for comprehensive error detection, while the second-stage DCI uses a shorter CRC or no CRC since it benefits from the association with the first stage and has fewer blind decoding operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11026244B2Method and device in terminal and base station for dynamic scheduling
Publication Date: 2021.06.01 HONOR DEVICE CO LTD
  • US11026244B2 patent drawing
  • US11026244B2 patent drawing
  • US11026244B2 patent drawing

AI summary

The disclosure provides a method and a device in a terminal and a base station for dynamic scheduling. The UE detects a first bit block in a first time-frequency resource set and a second bit block in a second time-frequency resource set. The first bit block includes a first and a second bit sub-block, the first bit sub-block is for generating the second bit sub-block. The second bit block includes a third and a fourth bit sub-block, and the third bit sub-block is for generating the fourth bit sub-block; or the second bit block includes a third bit sub-block which does not include CRC bits. The first and the second bit block are associated. Bits in the second bit sub-block is greater than bits in the fourth bit sub-block. The disclosure effectively reduce number of check bits in control signalings, thereby reducing overheads of control signalings and improving spectrum efficiency.