Dynamic Allocated Scrubbing for DRAM Error Control
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Solution Overview
Problem
The increasing bit errors and decreasing yield of DRAMs due to shrinking fabrication design rules pose challenges in maintaining the reliability and efficiency of semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit, and a control logic circuit that performs dynamic allocated scrubbing (DAS) operations on weak codewords with a shorter period than normal scrubbing, reducing error bit accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal scrubbing operation is performed on all memory cell rows with a fixed period, then the scrubbing coverage is comprehensive, but error bits in weak codewords accumulate faster
Solution Approach 1:
The patent applies local quality by differentiating scrubbing periods based on codeword strength. Weak codewords (those with higher error susceptibility) receive more frequent scrubbing with a second period, while strong codewords use the first period. This localized adjustment of scrubbing frequency to specific memory locations optimizes error detection efficiency without uniformly increasing the scrubbing burden across all memory cell rows.
Solution Approach 2:
The patent implements dynamics by making the scrubbing period adaptive rather than fixed. The scrubbing control circuit dynamically adjusts the scrubbing period based on codeword strength characteristics identified during normal operations. Weak codewords trigger a shorter second period for more frequent scrubbing, while strong codewords maintain the longer first period, allowing the system to adapt scrubbing intensity to actual error susceptibility.
2Reliability
If scrubbing operation frequency is increased to reduce error bit accumulation, then reliability improves, but power consumption and operational overhead increase
Solution Approach 1:
The patent reduces overall power consumption by applying increased scrubbing frequency only to weak codewords rather than uniformly to all memory cell rows. The scrubbing control circuit identifies weak codewords and applies the shorter second period only to those specific locations, while strong codewords continue to use the energy-efficient first period. This localized approach minimizes the total energy overhead of enhanced error prevention.
3Reliability
If dynamic allocated scrubbing is implemented to perform scrubbing on weak codewords with shorter period, then error bit accumulation is reduced, but device complexity increases
Solution Approach 1:
The scrubbing control circuit is designed with multi-functionality to handle both normal scrubbing operations and dynamic allocated scrubbing operations within a single unified structure. The same circuit generates scrubbing addresses, controls scrubbing timing, and manages the distinction between first and second periods based on codeword strength. This universal design avoids the need for separate dedicated circuits for different scrubbing modes, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows, and each of the memory cell rows including volatile memory cells. The scrubbing control circuit generates scrubbing addresses for performing a normal scrubbing operation on the memory cell rows with a first period based on refresh row addresses for refreshing the memory cell rows. The control logic circuit controls the ECC engine the scrubbing control circuit to distribute a scrubbing operation on weak codewords dynamically within the refresh operation such that a dynamic allocated scrubbing (DAS) operation is performed with a second period smaller than the first period. An error bit is detected in each of the weak codewords during the normal scrubbing operation or normal read operation on at least one of the memory cell rows.