Dynamic Sense Amplifier Address Grouping for Non-Volatile Memory
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Solution Overview
Problem
In non-volatile semiconductor memory systems, there is a challenge in minimizing power consumption while maintaining sufficient speed, especially in devices like cellular telephones and digital cameras, where not all bits are programmed during every sense amplifier address cycle, leading to inefficiencies in memory operations.
Innovation Solution
A non-volatile memory system evaluates user data to group sense amplifier addresses for writing in one cycle, comparing the number of bits to be programmed with an allowable number of parallel bits, and generates bitmap data to organize these groups, allowing for efficient programming within the allowable limits, thereby reducing power consumption and increasing write bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential programming methods are used, then power consumption is reduced, but write bandwidth and programming speed deteriorate
Solution Approach 1:
The patent implements dynamic address grouping that adapts the programming configuration based on the actual data pattern. The system dynamically determines which sense amplifier addresses should be grouped together in each cycle, optimizing the balance between parallel programming efficiency and power consumption based on real-time data characteristics rather than using a fixed sequential or parallel approach.
Solution Approach 2:
The patent segments the sense amplifier addresses into multiple groups, where each group can be programmed in parallel within a single address cycle. By dividing the address space into manageable groups and selectively activating only the necessary groups based on data requirements, the system achieves higher write bandwidth while maintaining power efficiency through selective parallel operation.
2Productivity
If all sense amplifier addresses are programmed in parallel, then write bandwidth increases, but power consumption exceeds allowable limits
Solution Approach 1:
The patent applies partial action by programming only the necessary subset of sense amplifier addresses in parallel during each address cycle, rather than activating all addresses. The system determines the optimal number of groups to activate based on data patterns, performing just enough parallel programming to meet bandwidth requirements while staying within power consumption limits.
Solution Approach 2:
The system dynamically adjusts the degree of parallelism by varying the number of address groups activated in each cycle based on real-time data characteristics. This dynamic control allows the system to optimize the trade-off between write bandwidth and power consumption, activating more groups when bandwidth is critical and fewer groups when power savings are prioritized.
3Productivity
If sense amplifier addresses are grouped for parallel programming, then write bandwidth increases, but system complexity increases
Solution Approach 1:
The patent segments the address grouping control into manageable units, where addresses are divided into groups that can be independently controlled. This segmentation simplifies the control logic by breaking down the complex task of managing all possible address combinations into smaller, more manageable group control operations.
Solution Approach 2:
The system performs preliminary analysis of the data pattern before programming to pre-determine the optimal address grouping configuration. By evaluating data characteristics in advance and pre-calculating the best grouping strategy, the system reduces the complexity of real-time control decisions during the actual programming operation.
Data Source
AI summary
A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.