Dynamic SerDes Link Adjustment via Synchronization Word
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Solution Overview
Problem
Current high-speed serial link solutions, such as SerDes, face challenges in dynamically adjusting bandwidth to meet increasing demands, leading to network delays due to time-consuming synchronization and alignment processes.
Innovation Solution
A method involving sending link information to enable additional SerDes links, using a short unit frame period for synchronization with padding data and synchronization words, and switching to a long unit frame period for data alignment, allowing for real-time synchronization and alignment without interrupting service data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple SerDes links are used to transmit data in parallel to achieve high bandwidth, then bandwidth requirement is satisfied, but dynamic adjustment capability is limited and network delay increases during link adjustment
Solution Approach 1:
The patent applies preliminary action by pre-configuring synchronization and alignment operations before actual data transmission begins. When a SerDes link is dynamically added, the system performs synchronization and alignment procedures in advance using test patterns and synchronization words, so that when the link is ready for production traffic, all timing and phase adjustments are already complete. This eliminates delays during actual data transmission.
Solution Approach 2:
The patent segments the link adjustment process into distinct phases: initialization phase with synchronization words, alignment phase with alignment markers, and production phase with actual data transmission. Each phase uses specific protocols and procedures tailored to its requirements, allowing optimization of each segment independently while maintaining overall system performance.
2Reliability
If synchronization and alignment operations are performed according to preset protocol during dynamic adjustment, then communication transmission accuracy is ensured, but adjustment time increases causing large network delay
Solution Approach 1:
The patent implements periodic action by using regular intervals for synchronization word insertion and alignment marker transmission. The system transmits synchronization patterns at fixed periods during the initialization phase, allowing receiving end to reliably detect and lock onto the signal timing. This periodic structure ensures accurate synchronization while maintaining predictable and optimized adjustment timelines.
Solution Approach 2:
The patent uses synchronization words and alignment markers as intermediary elements that facilitate the transition from link establishment to production data transmission. These intermediary signals carry timing and phase information without requiring full production data protocols, enabling rapid and accurate link synchronization before actual communication begins.
3Productivity
If SerDes links are configured in advance to meet bandwidth requirements, then bandwidth capacity is sufficient, but adaptability to changing service demands is reduced
Solution Approach 1:
The patent applies dynamics by enabling SerDes links to be dynamically added or removed based on real-time bandwidth demands. The system monitors service requirements and can activate additional SerDes links when bandwidth capacity is insufficient, or deactivate links when demand decreases. This dynamic configuration allows the system to adapt to changing traffic patterns while maintaining optimal performance.
Solution Approach 2:
The patent changes the operational parameter of SerDes links from static pre-configuration to dynamic on-demand activation. By controlling the enable/disable state of individual SerDes links based on bandwidth requirements, the system can adjust total capacity in discrete steps, providing fine-grained control over resource allocation and improving adaptability to varying service demands.
Data Source
AI summary
A receiving-side chip is disclosed according to the present invention, which includes a processor, configured to acquire and execute following instructions: receiving link information sent by a sending-side chip, and enabling, according to the link information, a SerDes link to be added; receiving padding data from the added SerDes link according to a short unit frame period to acquire a synchronization word, and determining, according to the synchronization word, whether the added SerDes link has been synchronized; switching a read period of data in the added SerDes link from the short unit frame period into a long unit frame period, and aligning the data of the added SerDes link with the data of an original SerDes link; and receiving service data over the added SerDes link and the original SerDes link.