Dynamic Serializer Clock Division for Unified Parallel Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high-speed transmitting apparatuses require separate serializer circuits for different parallel interfaces due to varying data widths, necessitating additional hardware for accommodating diverse parallel interfaces in applications like HDMI, PCIe, and USB.
Innovation Solution
A transmitting apparatus with a dynamic divider circuit that generates a parallel clock signal based on a variable division input, allowing it to unify parallel interfaces by shifting variable parallel data into a bit stream and outputting a serial bit stream using a multiplexer, eliminating the need for multiple serializer circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate serializer circuits are used for different parallel interfaces, then each interface can be supported with dedicated hardware, but the device complexity and hardware requirements increase
Solution Approach 1:
The patent implements a universal serializer circuit that can handle multiple parallel interfaces (HDMI, PCIe, USB, DP) with different data widths (8, 10, 12, 16, 18, 20 bits) through a single unified architecture. The circuit uses configurable parameters and control logic to adapt to various interface requirements, eliminating the need for separate dedicated serializer circuits for each interface type.
Solution Approach 2:
The patent employs dynamic configuration capabilities within the serializer circuit, allowing it to adjust its operation based on the detected parallel interface type and data width. The circuit can dynamically reconfigure its internal logic, clock division ratios, and data path width to match the requirements of different interfaces, providing adaptability without requiring multiple static circuit designs.
2Adaptability or versatility
If separate serializer circuits are used for different data widths, then each data width can be optimized, but the hardware requirements and area increase
Solution Approach 1:
The patent creates a universal serializer circuit that supports multiple data widths (8, 10, 12, 16, 18, 20 bits) through a single unified architecture. The circuit uses configurable parameters and control logic to adapt to various interface requirements, eliminating the need for separate dedicated serializer circuits for each interface type.
Solution Approach 2:
The patent changes operational parameters such as clock division ratios, data path width, and control signal configurations to accommodate different data widths. By dynamically adjusting these parameters rather than creating separate hardware for each width, the circuit achieves support for varying data widths while minimizing area occupation.
3Adaptability or versatility
If multiple serializer circuits are implemented, then different parallel interfaces can be accommodated, but additional hardware is required
Solution Approach 1:
The patent merges the functionality of multiple separate serializer circuits into a single unified serializer circuit. By combining the data paths, control logic, and clock management resources into one shared circuit, the patent reduces the total quantity of hardware components while maintaining support for multiple parallel interfaces with different data widths.
Solution Approach 2:
The unified serializer circuit is designed to perform multiple functions across different interface types and data widths, replacing what would traditionally require multiple specialized circuits. This multi-functional approach significantly reduces the overall hardware component count.
Data Source
AI summary
Various example embodiments relate to unifying a plurality of parallel interfaces. A transmitting apparatus configured to serialize parallel bits implements a dynamic divider circuit for loading varying parallel bits into the transmitting apparatus. An input clock generator is configured to generate a desired and/or predefined clock frequency. The dynamic divider circuit receives the desired and/or predefined clock frequency and generates a parallel clock frequency by dividing the desired and/or predefined clock frequency based on a variable division input. Number of parallel bits loaded into the transmitting apparatus is based on the generated parallel clock frequency. Further, a shift register generates a bit stream from the parallel bits loaded into the shift register and the generated bit stream is converted to serial bit by a multiplexer.