Dynamic Set Associative Cache for Multitask Contention

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Solution Overview

Problem

Existing cache systems for multitask OS, multiprocessor, and multithread environments face cache mishits due to fixed cache configurations, leading to inefficient use of cache resources and reduced performance when the number of sets and ways are changed.

Innovation Solution

A set associative cache system that dynamically adjusts the number of sets and ways while maintaining the same cache block locations and capacity, using a set selecting section, way selecting section, decision section, and replacement selecting section based on cache management information and LRU data to optimize cache usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the number of ways is fixed for each process unit, then the cache configuration is simple, but the number of ways may not be sufficient for process units with many cache requests

Engineering Contradiction:
Improvecache configuration complexityVSAvoidcache request handling capability
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements dynamic way allocation where the number of ways assigned to each process unit is not fixed but can be adjusted based on the current number of active process units. The way selecting section dynamically determines which ways are allocated to which process units, allowing the cache system to adapt to varying workload demands and prevent cache mishits when multiple process units contend for cache resources.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of way allocation based on the number of process units. When the number of process units increases, the cache configuration transitions from a fixed way allocation to a dynamic allocation scheme where the way selecting section redistributes ways among process units, thereby maintaining adequate cache capacity per process unit while utilizing the full cache resource pool.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the number of ways is made variable to increase capacity, then more cache requests can be handled, but most ways are used by the same process unit and other process units cannot use the cache

Engineering Contradiction:
Improvecache request handling capabilityVSAvoidmulti-process unit cache sharing
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The way selecting section uses feedback from the process unit identification section to determine which process unit is currently accessing the cache and dynamically allocates ways accordingly. This feedback mechanism ensures that when multiple process units are active, their cache accesses are properly distributed across different ways, preventing one process unit from monopolizing all ways and enabling effective multi-process unit cache sharing.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The cache ways are designed to be universally allocatable to any process unit based on dynamic selection rather than being dedicated to specific process units. The way selecting section enables each way to serve multiple process units as needed, allowing the cache system to function effectively for any combination of active process units and improving overall system adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If cache region is divided by cache set, then cache region can be allocated to each process unit, but different process units cannot use a cache block directly causing cache mishit

Engineering Contradiction:
Improvecache region allocationVSAvoidcache hit ratio
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments the cache into sets and ways, with the set selecting section choosing specific sets based on the cache address and the way selecting section choosing specific ways within those sets. This segmentation allows flexible allocation of cache resources to different process units while maintaining the ability for any process unit to access any cache block through the appropriate set and way selection, thereby improving cache hit ratio while preserving allocation clarity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7330935B2Set associative cache system and control method for cache memories
Publication Date: 2008.02.12 NEC CORP
  • US7330935B2 patent drawing
  • US7330935B2 patent drawing
  • US7330935B2 patent drawing

AI summary

A cache system comprises i (e.g., 2) groups of m (e.g., 2) ways and n (e.g., 2) sets of cache arrays, a set address decoder, a comparator, a cache address and cache management information. The set address decoder selects all or one of the i groups of cache arrays based on the cache address and cache management information, and selects a j-th set in the selected cache memories according to the cache address. The comparator selects a way from the selected set based on the cache management information, compares the block address of a cache block in the selected way with a requested block address to decide whether there is a cache hit or a miss, and select a replacement block based on LRU information