Dynamic Shift Test Pattern Compression
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Solution Overview
Problem
As integrated circuit feature size shrinks, the increasing number of functional blocks on a single chip leads to a dramatic increase in test data volume and test application time, with existing test compression schemes struggling to efficiently utilize limited tester bandwidth, resulting in undetected faults due to reduced encoding capacity.
Innovation Solution
The method involves generating compressed test patterns by adding non-shift clock cycles to specific segments of scan chains, allowing the decompressor to generate additional bits and store information related to these cycles, thereby improving test compression efficiency without increasing channel inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of channel inputs is reduced to test more cores in parallel, then tester bandwidth utilization improves and more cores can be tested simultaneously, but the encoding capacity decreases causing testable faults to become undetected
Solution Approach 1:
The scan chains are divided into multiple segments, and non-shift clock cycles are selectively added to specific segments that require additional encoding capacity. This segmentation allows different parts of the circuit to use different numbers of clock cycles, optimizing both the number of cores that can be tested in parallel and the fault detection capability for each segment.
Solution Approach 2:
The patent implements dynamic allocation of clock cycles by adding non-shift clock cycles selectively to segments based on their compression requirements. This dynamic approach allows the system to adaptively allocate resources, increasing encoding capacity where needed while maintaining high parallel testing efficiency in other segments.
2Quantity of substance
If non-shift clock cycles are added to increase encoding capacity, then more specified bits can be compressed, but the test application time increases
Solution Approach 1:
Instead of uniformly adding non-shift clock cycles to all segments, the patent applies them locally only to segments that have uncompressible test cubes. This local quality approach ensures that encoding capacity is increased only where necessary, minimizing the impact on test application time while achieving the required compression for difficult-to-compress segments.
Solution Approach 2:
The patent changes the parameter of clock cycle allocation dynamically, adding non-shift clock cycles to specific segments based on their compression needs. This parameter change allows the system to optimize encoding capacity for segments with high specified bit density while keeping the overall test application time close to the original shift-in time.
3Adaptability or versatility
If dedicated control signals are added for each core to control channel input configuration, then dynamic allocation of channel inputs becomes possible, but the device complexity increases and it does not scale well for large numbers of cores
Solution Approach 1:
The patent uses a universal control mechanism where a single control signal line can dynamically configure channel inputs for multiple cores. Instead of dedicating control signals to each core, the system uses a multi-functional control approach where the same control infrastructure serves all cores, reducing complexity while maintaining adaptability.
Solution Approach 2:
The patent implements partial dynamic allocation by using a limited set of control signals that can configure channel inputs for multiple cores rather than full per-core control. This partial action approach provides sufficient flexibility for dynamic channel allocation without the excessive complexity of dedicated control signals for each core.
Data Source
AI summary
Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.