Dynamic SIMD Width Allocation for Vector Instruction Register Optimization
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Solution Overview
Problem
Current compilers allocate fixed register memory for vector instructions, limiting the number of parallel threads that can run and slowing down execution speed due to inefficient memory utilization.
Innovation Solution
A method and system that dynamically analyze intermediate representation code to classify instructions as vector instructions and dynamically set Single Instruction Multiple Data (SIMD) width for each, allowing for optimized register allocation and creation of super registers to allocate physical registers effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed register memory allocation is used for vector instructions, then implementation simplicity is maintained, but the number of parallel threads is limited and execution speed decreases
Solution Approach 1:
The patent implements dynamic SIMD width selection that adapts to the specific characteristics of each vector instruction. The compiler analyzes vector instructions and dynamically determines the appropriate SIMD width (e.g., 4, 8, 16, 32) based on data size and instruction type, rather than using a fixed allocation. This dynamic approach enables more efficient parallel thread execution while maintaining manageable complexity through systematic analysis rules.
Solution Approach 2:
The patent changes the parameter of SIMD width from a fixed value to a dynamically determined value. By analyzing vector instructions and adjusting the SIMD width parameter accordingly, the system optimizes register memory allocation to support more parallel threads. The compiler modifies the SIMD width parameter based on instruction characteristics, enabling flexible adaptation to different computational requirements.
2Productivity
If dynamic SIMD width setting is implemented, then more parallel threads can run and execution speed increases, but compiler complexity increases
Solution Approach 1:
The patent segments the compiler into distinct functional modules: vector instruction identification, SIMD width determination, and register allocation. Each module performs a specific task in the dynamic allocation process. The compiler analyzes vector instructions, determines appropriate SIMD widths based on segmentation of the analysis process, and allocates registers systematically. This modular segmentation manages compiler complexity while enabling dynamic optimization for more parallel threads.
Solution Approach 2:
The patent performs preliminary analysis of vector instructions during the compilation phase to determine optimal SIMD widths before code generation. The compiler pre-processes vector instructions, identifies their characteristics, and determines the appropriate SIMD width in advance. This preliminary action enables the generated code to efficiently utilize more parallel threads during execution without adding runtime complexity.
Data Source
AI summary
The present disclosure relates to a system and a method of optimizing register allocation by a processor. The method comprising receiving an intermediate representation (IR) code of a source code and initializing single instruction multiple data (SIMD) width for the IR code. The method comprising analyzing each basic block of the IR code to classify determine one or more instructions of the IR code as vector instructions, wherein each basic block is one of LOAD, STORE and arithmetic logical and multiply (ALM) instructions. The method comprising dynamically setting the SIMD width for each of the vector instructions.