Dynamic Synchronization for Parallel Circuit Simulation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current event-level simulation techniques require all threads to synchronize at the same simulation time, which is inefficient for timing designs with staggered event activity, leading to reduced parallelism and increased costs due to backtracking and state restoration in GLS timing simulations.

Innovation Solution

The proposed solution involves calculating a minimum delay (minDelay) and causal delay (CausalDelay) for event blocks to determine a next synchronization point, allowing threads to execute asynchronously and synchronize only when necessary, eliminating the need for cross-thread communication and state restoration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all threads synchronize at the same simulation time, then simulation correctness is ensured, but parallelism is reduced and CPU core utilization is poor

Engineering Contradiction:
Improvesimulation correctnessVSAvoidparallelism
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic synchronization where threads can execute at different simulation times and synchronize only when necessary. The synchronization mechanism adapts to the actual event timing rather than forcing all threads to wait at every simulation time step, allowing threads to proceed asynchronously when no synchronization is needed and maintaining correctness only when events require coordination.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the simulation execution into independent event blocks that can be processed by different threads at different times. By dividing the simulation workload into discrete event segments with explicit synchronization points only where needed, the system allows parallel execution of independent segments while maintaining correctness at segment boundaries.

Inventive Principle:
Principle #1Segmentation

2Productivity

If threads execute asynchronously at different simulation times, then parallelism and CPU core utilization are improved, but synchronization complexity increases

Engineering Contradiction:
ImproveCPU core utilizationVSAvoidsynchronization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The synchronization mechanism serves itself by automatically determining when synchronization is needed based on event timing and thread state. The system self-manages the synchronization points without requiring external coordination or complex control logic, as threads naturally synchronize when they encounter events that require coordination with other threads.

Inventive Principle:
Principle #25Self-service

3Productivity

If synchronization points are reduced, then parallelism is improved, but simulation correctness may be compromised

Engineering Contradiction:
ImproveparallelismVSAvoidsimulation correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary analysis to identify exactly where synchronization is needed before execution. By pre-determining synchronization points based on event dependencies and timing relationships, the system ensures correctness is maintained at critical points while avoiding unnecessary synchronization elsewhere, thus maximizing parallelism without compromising correctness.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11327790B1Event-level parallel simulation using dynamic synchronization
Publication Date: 2022.05.10 SYNOPSYS INC
  • US11327790B1 patent drawing
  • US11327790B1 patent drawing
  • US11327790B1 patent drawing

AI summary

The independent claims of this patent signify a concise description of embodiments. A method is provided for parallel simulation using synchronization during simulation. The method comprises executing a plurality of threads in parallel, identifying a first event block and a second event block of a circuit design, calculating a minimum delay (minDelay) based on a current simulation time, scheduled times for execution of the first event block and the second event block, and causal delays (CausalDelay) of the first event block and the second event block, and scheduling a next synchronization point based on the minimum delay, the next synchronization point being a next simulation time at which the plurality of threads synchronize to a common clock. This Abstract is not intended to limit the scope of the claims.