Dynamic Skew Correction in Multi-Lane Communication Links
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Solution Overview
Problem
Conventional methods for addressing dynamic skew in multi-lane communication links are not optimal, leading to cyclic redundancy code errors, link re-initialization, and degraded performance due to variations in process, voltage, and temperature, as well as differences in SKIP ordered sets and idle cycles across lanes.
Innovation Solution
A receiver unit with a first-in first-out (FIFO) unit and alignment logic that dynamically compensates for differing numbers of symbols in SKIP ordered sets and asynchronous idle cycles by generating dummy alignment symbols and adjusting storage buffer depth, ensuring synchronization across all lanes without requiring additional hardware or vendor guarantees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to address dynamic skew, then link stability is maintained through re-initialization, but link performance degrades and CRC errors increase
Solution Approach 1:
The patent implements dynamic skew correction by making the FIFO buffer depth adjustable and controllable in real-time. The buffer depth is dynamically modified based on detected skew conditions, allowing the system to adapt to varying skew scenarios without re-initialization, thus maintaining both link stability and performance
Solution Approach 2:
The patent employs a feedback mechanism where the receiver detects skew conditions by monitoring alignment symbols and sends skew correction commands back to the transmitter. This closed-loop feedback system enables continuous skew compensation during active data transfer, preventing CRC errors and maintaining link performance
2Reliability
If buffer hardware is added to compensate for dynamic skew, then skew correction capability is improved, but device complexity increases
Solution Approach 1:
Instead of adding multiple fixed-depth buffers, the patent uses a single FIFO buffer whose depth is dynamically modified through control signals. This approach achieves skew compensation functionality without increasing hardware complexity, as the same buffer structure serves multiple depth configurations
Solution Approach 2:
The patent changes the operational parameter of the FIFO buffer (buffer depth) rather than adding more hardware resources. By dynamically adjusting the buffer depth parameter through control logic, the system achieves skew correction capability without increasing device complexity
3Reliability
If re-initialization is forced to address dynamic skew, then link stability is restored, but loss of time occurs due to re-training
Solution Approach 1:
The patent prepares for skew correction by continuously monitoring alignment symbols and detecting skew conditions before they cause CRC errors. By taking preliminary detection and correction actions during normal operation, the system prevents the need for time-consuming re-initialization and re-training sequences
4Measurement precision
If static skew correction techniques are used during link training, then static skew is corrected, but dynamic skew occurring during active state is not addressed
Solution Approach 1:
The patent transitions from static skew correction (fixed during link training) to dynamic skew correction (adjustable during active state). The FIFO buffer depth and skew correction commands are continuously adjustable based on real-time skew conditions, enabling the system to handle both static and dynamic skew scenarios
Solution Approach 2:
The patent implements a feedback mechanism that operates during the active state to detect and correct dynamic skew. By monitoring alignment symbols in real-time and adjusting FIFO buffer depth based on detected skew, the system gains adaptability to handle dynamic skew conditions that static correction techniques cannot address
Data Source
AI summary
A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.