Dynamic SLC Buffer Conversion for Storage Performance
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Solution Overview
Problem
Conventional solutions for converting tri-level cell (TLC) memory regions to single-level cell (SLC) memory regions and back are inefficient, leading to suboptimal performance and failure to meet quality of service (QOS) constraints in storage devices.
Innovation Solution
A memory structure that converts multi-level cell (MLC) regions into dynamic SLC regions by reducing voltage levels, allowing for improved write bandwidth, and gradually evicts data from dynamic SLC regions to MLC regions based on a programmable eviction ratio, ensuring consistent performance and meeting QOS constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TLC memory is used to increase storage capacity, then storage capacity is improved, but access speed deteriorates
Solution Approach 1:
The memory system is segmented into multiple pools including SLC buffer pool, TLC pool, and dirty pool. The SLC buffer pool is specifically designated for high-speed write operations while TLC pool provides high-capacity storage. This segmentation allows the system to simultaneously achieve fast access speeds in the SLC region and high storage capacity in the TLC region, resolving the contradiction between speed and capacity.
2Quantity of substance
If conventional conversion policies are used to convert TLC to SLC, then SLC buffer capacity is maintained, but performance and QOS constraints are not met
Solution Approach 1:
The patent implements dynamic conversion policies that adaptively convert TLC blocks to SLC blocks based on real-time system conditions, QOS constraints, and workload characteristics. The conversion is not static but dynamically adjusted through a state machine that monitors buffer occupancy, write bandwidth requirements, and QOS parameters. This dynamic approach ensures optimal write bandwidth while maintaining sufficient SLC buffer capacity to meet QOS constraints.
Solution Approach 2:
The system changes key parameters including conversion ratios, voltage levels (from 8 levels in TLC to fewer levels in SLC), and buffer allocation based on system state. By varying these parameters dynamically, the system can shift between high-capacity TLC mode and high-performance SLC mode as needed, resolving the contradiction between maintaining buffer capacity and achieving high productivity.
3Quantity of substance
If more voltage levels are used in TLC memory, then storage capacity per cell is improved, but access speed deteriorates
Solution Approach 1:
The SLC buffer pool acts as an intermediary between the host system and the TLC storage pool. High-speed write operations are directed to the SLC buffer where data can be programmed quickly with fewer voltage levels. The SLC buffer then gradually fills the TLC pool at optimized speeds. This intermediary approach allows the system to achieve high program speeds for incoming data while ultimately storing data in high-capacity TLC cells.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.