Dynamic SLC Cache Size Adjustment for Flash Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing flash memory devices have a fixed cache size that reduces user data capacity and efficiency, as a portion of memory is dedicated to a temporary SLC cache, limiting the storage of user data and diminishing performance when the cache becomes full.

Innovation Solution

Implementing a dynamic SLC memory cache that adjusts its size based on available memory space, allowing blocks to dynamically switch between SLC and MLC modes, optimizing cache usage and reallocating memory as needed to prevent data corruption during programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed size SLC cache is used to improve memory reliability and performance, then cache performance is improved, but user data capacity is reduced

Engineering Contradiction:
Improvememory reliabilityVSAvoiduser data capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements a dynamic SLC cache mechanism where the cache size is not fixed but can be adjusted based on available memory space. The controller dynamically determines the optimal cache size and reallocates memory blocks between SLC cache and MLC user data storage, allowing the system to adapt to different storage conditions and maximize both reliability and user capacity simultaneously.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If a fixed portion of memory is dedicated to SLC cache, then cache functionality is ensured, but storage efficiency for user data is reduced

Engineering Contradiction:
Improvecache functionalityVSAvoidstorage efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system changes the parameter of cache size dynamically rather than keeping it fixed. The controller monitors available memory space and adjusts the SLC cache size parameter accordingly, allowing the cache to occupy only the necessary portion of memory while maximizing user data storage efficiency.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If cache size is increased to improve performance, then memory performance is improved, but available user capacity is reduced

Engineering Contradiction:
Improvememory performanceVSAvoiduser capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent makes the cache size dynamic rather than static, allowing it to expand or contract based on system needs. When performance is prioritized, the cache can grow; when user capacity is needed, the cache shrinks. This dynamic adjustment resolves the contradiction by making cache size adaptable rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system dynamically changes the cache size parameter based on available memory space and performance requirements, allowing optimization of both memory performance and user capacity at different times rather than being constrained by a fixed parameter.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2715548B1Dynamic memory cache size adjustment in a memory device
Publication Date: 2019.10.30 MICRON TECHNOLOGY INC
  • EP2715548B1 patent drawingFigure 1
  • EP2715548B1 patent drawingFigure 2
  • EP2715548B1 patent drawingFigure 3

AI summary

Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.