Dynamic SLC-MLC Memory Block Mode Switching
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Solution Overview
Problem
Existing memory systems face challenges in optimizing the balance between data storage capacity and endurance (number of erase/write cycles) due to the trade-off between single-level cell (SLC) and multi-level cell (MLC) modes, where SLC modes offer higher endurance but lower capacity, and MLC modes provide greater capacity but reduced endurance.
Innovation Solution
A memory system and operation method that dynamically switch memory blocks between SLC and MLC modes based on usage thresholds, selecting victim blocks in MLC mode when memory usage exceeds a certain threshold and switching them to SLC mode when usage is low, thereby optimizing endurance and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory blocks are operated in SLC mode, then endurance (number of erase/write cycles) is improved, but storage capacity is reduced
Solution Approach 1:
The patent implements dynamic mode switching between SLC and MLC for memory blocks based on real-time monitoring of memory usage and access patterns. The controller adjusts the operational mode of each memory block dynamically, transitioning from static to adaptive operation to optimize both endurance and capacity utilization according to system demands.
Solution Approach 2:
The patent changes the operational parameters of memory blocks by switching between SLC and MLC modes based on monitored conditions such as memory usage thresholds and access frequency. This parameter adjustment allows the system to adapt the characteristics of memory blocks (endurance vs. capacity) according to current operational requirements.
2Quantity of substance
If memory blocks are operated in MLC mode, then storage capacity is improved, but endurance is reduced
Solution Approach 1:
The controller dynamically adjusts the operational mode of memory blocks based on monitored memory usage and access patterns. When memory usage is low or access patterns indicate infrequent writes, MLC mode is activated to maximize storage capacity. When usage thresholds are exceeded or write intensity increases, the system transitions to SLC mode to preserve endurance.
Solution Approach 2:
The patent changes operational parameters by switching memory blocks between MLC and SLC modes based on monitored conditions. This allows the system to adjust the capacity-endurance tradeoff dynamically, selecting MLC for high-capacity needs and SLC for high-endurance requirements.
3Reliability
If all memory blocks are switched to SLC mode to extend lifetime, then endurance is improved, but available storage capacity is reduced
Solution Approach 1:
The patent applies different operational modes to different memory blocks based on their specific usage characteristics. Instead of uniformly switching all blocks to SLC mode, the controller identifies individual blocks that benefit from SLC mode (those with high write intensity or critical data) while maintaining MLC mode for blocks with lower write demands, thereby preserving overall system lifetime while maximizing available capacity.
Solution Approach 2:
The memory device is segmented into multiple blocks that can operate independently in different modes. This segmentation allows the system to apply SLC mode selectively to specific blocks that require enhanced endurance while keeping other blocks in MLC mode for maximum capacity utilization.
Data Source
AI summary
A memory system may include: a memory device including a plurality of memory blocks which includes memory cells supporting a two-or-more-level cell (XLC) mode and a single level cell (SLC) mode; and a controller suitable for managing data of the memory device and controlling the memory device, wherein, when memory usage of the memory device is greater than or equal to a first threshold value, the controller selects one or more free memory blocks as one or more victim memory blocks, switches a mode of each victim memory block to the XLC mode, and moves data stored in a source memory block to the one or more victim memory blocks, wherein the source memory block, among the plurality of memory blocks, has data stored therein driven in the SLC mode.